[coreboot-gerrit] Patch set updated for coreboot: nyan: Fix timestamps and CBFS SPI integration
Patrick Georgi (pgeorgi@google.com)
gerrit at coreboot.org
Sat Feb 27 00:31:00 CET 2016
Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13832
-gerrit
commit e276f102427dda298d7a9142ec8db6ac8152efc1
Author: Julius Werner <jwerner at chromium.org>
Date: Wed Feb 17 16:12:46 2016 -0800
nyan: Fix timestamps and CBFS SPI integration
Nyan is an old board that was committed before several core code
modernizations to timestamp and CBFS code. Not all of those later
patches were correctly integrated with old boards like this, and the
core code has evolved to a point where it doesn't actually boot anymore.
This patch fixes that issue and brings the Nyan boards more in line with
how later ARM platforms look.
BRANCH=None
BUG=None
TEST=My Blaze boots again.
Change-Id: I3277a2f59ad8ed47063f7f6b556685313b1446f8
Signed-off-by: Patrick Georgi <pgeorgi at google.com>
Original-Commit-Id: 6a1679e342a7adc2b2371b6e3f69a898a7a5c717
Original-Change-Id: I2a0a2abbd79b4b5f756125dcbb6cbd9441016d4e
Original-Signed-off-by: Julius Werner <jwerner at chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/328543
Original-Reviewed-by: David Hendricks <dhendrix at chromium.org>
---
src/mainboard/google/nyan/Kconfig | 3 +
src/mainboard/google/nyan_big/Kconfig | 3 +
src/mainboard/google/nyan_blaze/Kconfig | 3 +
src/soc/nvidia/tegra124/bootblock.c | 3 +
src/soc/nvidia/tegra124/include/soc/memlayout.ld | 3 +-
src/soc/nvidia/tegra124/spi.c | 92 ------------------------
6 files changed, 14 insertions(+), 93 deletions(-)
diff --git a/src/mainboard/google/nyan/Kconfig b/src/mainboard/google/nyan/Kconfig
index 8f0c9de..d03f4d7 100644
--- a/src/mainboard/google/nyan/Kconfig
+++ b/src/mainboard/google/nyan/Kconfig
@@ -26,12 +26,15 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select MAINBOARD_DO_NATIVE_VGA_INIT
select BOARD_ROMSIZE_KB_4096
select SPI_FLASH
+ select SPI_FLASH_GIGADEVICE
+ select SPI_FLASH_WINBOND
select SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B
config CHROMEOS
select CHROMEOS_VBNV_EC
select EC_SOFTWARE_SYNC
select VIRTUAL_DEV_SWITCH
+ select COMMON_CBFS_SPI_WRAPPER
config MAINBOARD_DIR
string
diff --git a/src/mainboard/google/nyan_big/Kconfig b/src/mainboard/google/nyan_big/Kconfig
index b6f84f6..3ba61d5 100644
--- a/src/mainboard/google/nyan_big/Kconfig
+++ b/src/mainboard/google/nyan_big/Kconfig
@@ -27,12 +27,15 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select MAINBOARD_DO_NATIVE_VGA_INIT
select BOARD_ROMSIZE_KB_4096
select SPI_FLASH
+ select SPI_FLASH_GIGADEVICE
+ select SPI_FLASH_WINBOND
select SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B
config CHROMEOS
select EC_SOFTWARE_SYNC
select CHROMEOS_VBNV_EC
select VIRTUAL_DEV_SWITCH
+ select COMMON_CBFS_SPI_WRAPPER
config MAINBOARD_DIR
string
diff --git a/src/mainboard/google/nyan_blaze/Kconfig b/src/mainboard/google/nyan_blaze/Kconfig
index 0fd763d..07d3374 100644
--- a/src/mainboard/google/nyan_blaze/Kconfig
+++ b/src/mainboard/google/nyan_blaze/Kconfig
@@ -28,12 +28,15 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select MAINBOARD_DO_NATIVE_VGA_INIT
select BOARD_ROMSIZE_KB_4096
select SPI_FLASH
+ select SPI_FLASH_GIGADEVICE
+ select SPI_FLASH_WINBOND
select SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B
config CHROMEOS
select EC_SOFTWARE_SYNC
select CHROMEOS_VBNV_EC
select VIRTUAL_DEV_SWITCH
+ select COMMON_CBFS_SPI_WRAPPER
config MAINBOARD_DIR
string
diff --git a/src/soc/nvidia/tegra124/bootblock.c b/src/soc/nvidia/tegra124/bootblock.c
index cebe405..2a526a7 100644
--- a/src/soc/nvidia/tegra124/bootblock.c
+++ b/src/soc/nvidia/tegra124/bootblock.c
@@ -24,6 +24,7 @@
#include <soc/nvidia/tegra/apbmisc.h>
#include <soc/pinmux.h>
#include <soc/power.h>
+#include <timestamp.h>
#include <vendorcode/google/chromeos/chromeos.h>
static void run_next_stage(void *entry)
@@ -81,6 +82,8 @@ void main(void)
PINMUX_PWR_INT_N_FUNC_PMICINTR |
PINMUX_INPUT_ENABLE);
+ timestamp_init(0);
+
run_romstage();
}
diff --git a/src/soc/nvidia/tegra124/include/soc/memlayout.ld b/src/soc/nvidia/tegra124/include/soc/memlayout.ld
index c3f5f4e..5bab362 100644
--- a/src/soc/nvidia/tegra124/include/soc/memlayout.ld
+++ b/src/soc/nvidia/tegra124/include/soc/memlayout.ld
@@ -33,7 +33,8 @@ SECTIONS
STACK(0x4000E000, 8K)
BOOTBLOCK(0x40010000, 24K)
VERSTAGE(0x40016000, 72K)
- ROMSTAGE(0x40028000, 96K)
+ ROMSTAGE(0x40028000, 95K)
+ TIMESTAMP(0x4003FC00, 1K)
SRAM_END(0x40040000)
DRAM_START(0x80000000)
diff --git a/src/soc/nvidia/tegra124/spi.c b/src/soc/nvidia/tegra124/spi.c
index d5f7861..d5be4a6 100644
--- a/src/soc/nvidia/tegra124/spi.c
+++ b/src/soc/nvidia/tegra124/spi.c
@@ -798,69 +798,6 @@ int spi_xfer(struct spi_slave *slave, const void *dout,
return ret;
}
-#define JEDEC_READ 0x03
-#define JEDEC_READ_OUTSIZE 0x04
-#define JEDEC_FAST_READ_DUAL 0x3b
-#define JEDEC_FAST_READ_DUAL_OUTSIZE 0x05
-
-static struct spi_slave *boot_slave;
-
-static ssize_t tegra_spi_readat(const struct region_device *rdev, void *dest,
- size_t offset, size_t count)
-{
- u8 spi_read_cmd[JEDEC_FAST_READ_DUAL_OUTSIZE];
- unsigned int read_cmd_bytes;
- int ret = count;
- struct tegra_spi_channel *channel;
-
- channel = to_tegra_spi(boot_slave->bus);
-
- if (channel->dual_mode) {
- /*
- * Command 0x3b will interleave data only, command 0xbb will
- * interleave the address as well. It's nice to see the address
- * plainly when debugging, and we're mostly concerned with
- * large transfers so the optimization of using 0xbb isn't
- * really worthwhile.
- */
- spi_read_cmd[0] = JEDEC_FAST_READ_DUAL;
- spi_read_cmd[4] = 0x00; /* dummy byte */
- read_cmd_bytes = JEDEC_FAST_READ_DUAL_OUTSIZE;
- } else {
- spi_read_cmd[0] = JEDEC_READ;
- read_cmd_bytes = JEDEC_READ_OUTSIZE;
- }
- spi_read_cmd[1] = (offset >> 16) & 0xff;
- spi_read_cmd[2] = (offset >> 8) & 0xff;
- spi_read_cmd[3] = offset & 0xff;
-
- spi_claim_bus(boot_slave);
-
- if (spi_xfer(boot_slave, spi_read_cmd,
- read_cmd_bytes, NULL, 0) < 0) {
- ret = -1;
- printk(BIOS_ERR, "%s: Failed to transfer %u bytes\n",
- __func__, sizeof(spi_read_cmd));
- goto tegra_spi_cbfs_read_exit;
- }
-
- if (channel->dual_mode) {
- setbits_le32(&channel->regs->command1, SPI_CMD1_BOTH_EN_BIT);
- }
- if (spi_xfer(boot_slave, NULL, 0, dest, count)) {
- ret = -1;
- printk(BIOS_ERR, "%s: Failed to transfer %u bytes\n",
- __func__, count);
- }
- if (channel->dual_mode)
- clrbits_le32(&channel->regs->command1, SPI_CMD1_BOTH_EN_BIT);
-
-tegra_spi_cbfs_read_exit:
- /* de-assert /CS */
- spi_release_bus(boot_slave);
- return ret;
-}
-
struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs)
{
struct tegra_spi_channel *channel = to_tegra_spi(bus);
@@ -869,32 +806,3 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs)
return &channel->slave;
}
-
-static const struct region_device_ops tegra_spi_ops = {
- .mmap = mmap_helper_rdev_mmap,
- .munmap = mmap_helper_rdev_munmap,
- .readat = tegra_spi_readat,
-};
-
-static struct mmap_helper_region_device mdev =
- MMAP_HELPER_REGION_INIT(&tegra_spi_ops, 0, CONFIG_ROM_SIZE);
-
-const struct region_device *boot_device_ro(void)
-{
- return &mdev.rdev;
-}
-
-void boot_device_init(void)
-{
- struct tegra_spi_channel *boot_chan;
-
- boot_chan = &tegra_spi_channels[CONFIG_BOOT_MEDIA_SPI_BUS - 1];
- boot_chan->slave.cs = CONFIG_BOOT_MEDIA_SPI_CHIP_SELECT;
-
-#if CONFIG_SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B == 1
- boot_chan->dual_mode = 1;
-#endif
- boot_slave = &boot_chan->slave;
-
- mmap_helper_device_init(&mdev, _cbfs_cache, _cbfs_cache_size);
-}
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