[coreboot-gerrit] New patch to review for coreboot: Documentation/Intel: More CorebootPayloadPkg documentation
Leroy P Leahy (leroy.p.leahy@intel.com)
gerrit at coreboot.org
Sun Feb 28 15:47:22 CET 2016
Leroy P Leahy (leroy.p.leahy at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13851
-gerrit
commit 9f88c7b5dbb86958f68179afe29cd5a1de00ef78
Author: Lee Leahy <leroy.p.leahy at intel.com>
Date: Sun Feb 28 06:22:47 2016 -0800
Documentation/Intel: More CorebootPayloadPkg documentation
Add more documentation on the features that the EDK-II
CorebootPayloadPkg is using. Add 8254 and 8259 documentation
links. Add EDK-II documentation links.
TEST=Boot CorebootPayloadPkg to shell prompt
Change-Id: I66df1be0ba908b51b5ddb44a8671b2d7bdb46493
Signed-off-by: Lee Leahy <leroy.p.leahy at intel.com>
---
Documentation/Intel/SoC/quark.html | 4 +--
Documentation/Intel/SoC/soc.html | 54 +++++++++++++++++++++++++++++++++++-
Documentation/Intel/development.html | 13 ++++++++-
Documentation/Intel/index.html | 16 ++++++++++-
4 files changed, 82 insertions(+), 5 deletions(-)
diff --git a/Documentation/Intel/SoC/quark.html b/Documentation/Intel/SoC/quark.html
index ea704a9..5fe3f5c 100644
--- a/Documentation/Intel/SoC/quark.html
+++ b/Documentation/Intel/SoC/quark.html
@@ -47,7 +47,7 @@
<hr>
-<h1>Quark™ EDK2 CorebootPayloadPkg</h1>
+<h1><a name="CorebootPayloadPkg">Quark™ EDK2 CorebootPayloadPkg</a></h1>
<p>
Build Instructions:
</p>
@@ -214,6 +214,6 @@ Documentation:
<hr>
-<p>Modified: 20 February 2016</p>
+<p>Modified: 24 February 2016</p>
</body>
</html>
\ No newline at end of file
diff --git a/Documentation/Intel/SoC/soc.html b/Documentation/Intel/SoC/soc.html
index 5a0a442..2380cdf 100644
--- a/Documentation/Intel/SoC/soc.html
+++ b/Documentation/Intel/SoC/soc.html
@@ -33,6 +33,7 @@
</ol>
</li>
<li><a href="#AcpiTables">ACPI Tables</a></li>
+ <li><a href="#LegacyHardware">Legacy Hardware</a></li>
</ol>
@@ -560,7 +561,7 @@ Use the following steps to debug the call to TempRamInit:
<hr>
<h1><a name="AcpiTables">ACPI Tables</a></h1>
<p>
- One of the payloads that needs ACPI tables is the EDK2 CorebootPayloadPkg.
+ One of the payloads that needs ACPI tables is the EDK2 <a target="_blank" href="quark.html#CorebootPayloadPkg">CorebootPayloadPkg</a>.
</p>
<h2>FADT</h2>
@@ -664,6 +665,57 @@ Use the following steps to debug the call to TempRamInit:
</ol>
+
+<hr>
+<h1><a name="LegacyHardware">Legacy Hardware</a></h1>
+<p>
+ One of the payloads that needs legacy hardare is the EDK2 <a target="_blank" href="quark.html#CorebootPayloadPkg">CorebootPayloadPkg</a>.
+</p>
+
+<table border="1">
+ <tr bgcolor="c0ffc0">
+ <th>Peripheral</th>
+ <th>Use</th>
+ <th>8259 Interrupt Vector</th>
+ <th>IDT Base Offset</th>
+ <th>Interrupt Handler</th>
+ </tr>
+ <tr>
+ <td>
+ <a target="_blank" href="http://www.scs.stanford.edu/10wi-cs140/pintos/specs/8254.pdf">8254</a>
+ Programmable Interval Timer
+ </td>
+ <td>
+ EDK2: PcAtChipsetPkg/8254TimerDxe/<a target="_blank" href="https://github.com/tianocore/edk2/blob/master/PcAtChipsetPkg/8254TimerDxe/Timer.c">Timer.c</a>
+ </td>
+ <td>0</td>
+ <td>0x340</td>
+ <td>
+ <a target="_blank" href="https://github.com/tianocore/edk2/blob/master/PcAtChipsetPkg/8254TimerDxe/Timer.c#l71">TimerInterruptHandler</a>
+ </td>
+ </tr>
+ <tr>
+ <td>
+ <a target="_blank" href="https://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=1&cad=rja&uact=8&ved=0ahUKEwibxYKU3ZDLAhVOzWMKHfuqB40QFggcMAA&url=http%3A%2F%2Fbochs.sourceforge.net%2Ftechspec%2Fintel-8259a-pic.pdf.gz&usg=AFQjCNF1NT0OQ6ys1Pn6Iv9sv6cKRzZbGg&sig2=HfBszp9xTVO_fajjPWCsJw">8259</a>
+ Programmable Interrupt Controller
+ </td>
+ <td>
+ EDK2: PcAtChipsetPkg/8259InterruptControllerDxe/<a target="_blank" href="https://github.com/tianocore/edk2/blob/master/PcAtChipsetPkg/8259InterruptControllerDxe/8259.c">8259.c</a>
+ </td>
+ <td>
+ Master interrupts: 0, 2 - 7<br>
+ Slave interrupts: 8 - 15<br>
+ Interrupt vector 1 is never generated, the cascaded input generates interrupts 8 - 15
+ </td>
+ <td>
+ Master: 0x340, 0x350 - 0x378<br>
+ Slave: 0x380 - 0x3b8<br>
+ Interrupt descriptors are 8 bytes each
+ </td>
+ <td> </td>
+ </tr>
+</table>
+
<hr>
<p>Modified: 28 February 2016</p>
</body>
diff --git a/Documentation/Intel/development.html b/Documentation/Intel/development.html
index 74a476f..7b82321 100644
--- a/Documentation/Intel/development.html
+++ b/Documentation/Intel/development.html
@@ -125,6 +125,7 @@
<li>Payload and OS Features:
<ul>
<li><a target="_blank" href="SoC/soc.html#AcpiTables">ACPI Tables</a></li>
+ <li><a target="_blank" href="SoC/soc.html#LegacyHardware">Legacy hardware</a> support</li>
</ul>
</li>
</ul>
@@ -142,6 +143,16 @@
<th>Testing</th>
</tr>
<tr>
+ <td>8254 Programmable Interval Timer</td>
+ <td><a target="_blank" href="SoC/soc.html#LegacyHardware">Legacy hardware</a> support</td>
+ <td><a target="_blank" href="SoC/quark.html#CorebootPayloadPkg">CorebootPayloadPkg</a> gets to shell prompt</td>
+ </tr>
+ <tr>
+ <td>8259 Programmable Interrupt Controller</td>
+ <td><a target="_blank" href="SoC/soc.html#LegacyHardware">Legacy hardware</a> support</td>
+ <td><a target="_blank" href="SoC/quark.html#CorebootPayloadPkg">CorebootPayloadPkg</a> gets to shell prompt</td>
+ </tr>
+ <tr>
<td>Cache-as-RAM</td>
<td>
<a target="_blank" href="SoC/soc.html#TempRamInit">Find</a>
@@ -335,6 +346,6 @@
<hr>
-<p>Modified: 20 February 2016</p>
+<p>Modified: 24 February 2016</p>
</body>
</html>
\ No newline at end of file
diff --git a/Documentation/Intel/index.html b/Documentation/Intel/index.html
index 61d14c8..4d508bf 100644
--- a/Documentation/Intel/index.html
+++ b/Documentation/Intel/index.html
@@ -21,6 +21,7 @@
<h1>x86 coreboot Development</h1>
<ul>
+ <li>Get the <a target="_blank" href="https://www.coreboot.org/Git">coreboot source</li>
<li><a target="_blank" href="development.html">Overall</a> development</li>
<li><a target="_blank" href="fsp1_1.html">FSP 1.1</a> integration
</li>
@@ -28,10 +29,23 @@
<li><a target="_blank" href="Board/board.html">Board</a> support</li>
</ul>
+<h1>Payload Development</h1>
+<ul>
+ <li><a target="_blank" href="SoC/quark.html#CorebootPayloadPkg">CorebootPayloadPkg</a>
+ <ul>
+ <li><a target="_blank" href="https://github.com/tianocore/tianocore.github.io/wiki/EDK-II-Development-Process">EDK II Development Process</a></li>
+ <li>EDK II <a target="_blank" href="https://github.com/tianocore/tianocore.github.io/wiki/EDK%20II%20White%20papers">White Papers</a></li>
+ <li><a target="_blank" href="https://github.com/tianocore/tianocore.github.io/wiki/SourceForge-to-Github-Quick-Start">SourceForge to Github Quick Start</a></li>
+ <li>UEFI <a target="_blank" href="http://www.uefi.org/sites/default/files/resources/UEFI%20Spec%202_5_Errata_A.PDF">2.5 Errata A</a></li>
+ </ul>
+ </li>
+</ul>
+
+
+
<h1>Documentation</h1>
<ul>
<li><a target="_blank" href="http://www.uefi.org/sites/default/files/resources/ACPI_6.0.pdf">ACPI 6.0 Specification</a></li>
- <li>Get the <a target="_blank" href="https://www.coreboot.org/Git">coreboot source</li>
<li>Intel® 64 and IA-32 Architectures <a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-manual-325462.pdf">Software Developer Manual</a></li>
<li>Intel® Firmware Support Package External Architecture Specification <a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/fsp-architecture-spec-v1-1.pdf">V1.1</a></li>
</ul>
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