[coreboot-gerrit] Patch set updated for coreboot: soc/intel/apollolake: Add support for memory-mapped boot media

[Andrey Petrov (andrey.petrov@intel.com)]

Andrey Petrov (andrey.petrov at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13706

-gerrit

commit 0d2d0536f2654b86b3d7de5e9d319b6a727ab947
Author: Andrey Petrov <andrey.petrov at intel.com>
Date:   Fri Feb 12 15:12:43 2016 -0800

    soc/intel/apollolake: Add support for memory-mapped boot media
    
    On Apollo Lake SPI flash is memory mapped. The mapping is different
    to previous platforms. Only "BIOS" region is mapped in contrast to
    whole flash. Also, the 128 KiB right below 4 GiB are being decoded by
    readonly SRAM. Fail accesses to those regions, rather than returning
    false data.
    
    Change-Id: Iac3fa74cd221a5a46ceb34c2a79470290bcc2d84
    Signed-off-by: Andrey Petrov <andrey.petrov at intel.com>
---
 src/mainboard/intel/apollolake_rvp/Kconfig |  9 ++++
 src/soc/intel/apollolake/Kconfig           |  3 ++
 src/soc/intel/apollolake/Makefile.inc      |  3 ++
 src/soc/intel/apollolake/mmap_boot.c       | 74 ++++++++++++++++++++++++++++++
 4 files changed, 89 insertions(+)

diff --git a/src/mainboard/intel/apollolake_rvp/Kconfig b/src/mainboard/intel/apollolake_rvp/Kconfig
index 52d3777..9920b46 100644
--- a/src/mainboard/intel/apollolake_rvp/Kconfig
+++ b/src/mainboard/intel/apollolake_rvp/Kconfig
@@ -17,4 +17,13 @@ config MAINBOARD_VENDOR
 	string
 	default "Intel"
 
+config IFD_BIOS_END
+	hex
+	default 0x6FF000
+
+config IFD_BIOS_START
+	hex
+	default 0x1000
+
+
 endif
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index bb0cc20..401535f 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -80,4 +80,7 @@ config C_ENV_BOOTBLOCK_SIZE
 	hex
 	default 0x8000
 
+config X86_TOP4G_BOOTMEDIA_MAP
+	bool
+	default n
 endif
diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc
index 7f8beb0..17ddaec 100644
--- a/src/soc/intel/apollolake/Makefile.inc
+++ b/src/soc/intel/apollolake/Makefile.inc
@@ -11,17 +11,20 @@ bootblock-y += bootblock/bootblock.c
 bootblock-y += bootblock/cache_as_ram.S
 bootblock-y += bootblock/bootblock.c
 bootblock-y += gpio.c
+bootblock-y += mmap_boot.c
 bootblock-y += placeholders.c
 bootblock-y += tsc_freq.c
 bootblock-y += uart_early.c
 
 romstage-y += placeholders.c
 romstage-y += gpio.c
+romstage-y += mmap_boot.c
 romstage-y += uart_early.c
 
 smm-y += placeholders.c
 ramstage-y += placeholders.c
 ramstage-y += gpio.c
+ramstage-y += mmap_boot.c
 ramstage-y += uart_early.c
 
 CPPFLAGS_common += -I$(src)/soc/intel/apollolake/include
diff --git a/src/soc/intel/apollolake/mmap_boot.c b/src/soc/intel/apollolake/mmap_boot.c
new file mode 100644
index 0000000..3625924
--- /dev/null
+++ b/src/soc/intel/apollolake/mmap_boot.c
@@ -0,0 +1,74 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corp.
+ * (Written by Andrey Petrov <andrey.petrov at intel.com> for Intel Corp.)
+ * (Written by Alexandru Gagniuc <alexandrux.gagniuc at intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <boot_device.h>
+#include <cbfs.h>
+#include <commonlib/region.h>
+#include <console/console.h>
+#include <fmap.h>
+
+/* The 128 KiB right below 4G are decoded by readonly SRAM, not boot media */
+#define IFD_BIOS_MAX_MAPPED	(CONFIG_IFD_BIOS_END - 128 * KiB)
+#define IFD_MAPPED_SIZE		(IFD_BIOS_MAX_MAPPED - CONFIG_IFD_BIOS_START)
+#define IFD_BIOS_SIZE		(CONFIG_IFD_BIOS_END - CONFIG_IFD_BIOS_START)
+
+/*
+ *  If Apollo Lake is configured to boot from SPI flash "BIOS" region
+ *  (as defined in descriptor) is mapped below 4GiB.  Form a pointer for
+ *  the base.
+ */
+#define VIRTUAL_ROM_BASE ((uintptr_t)(0x100000000ULL - IFD_BIOS_SIZE))
+
+static const struct mem_region_device shadow_dev = MEM_REGION_DEV_INIT(
+	VIRTUAL_ROM_BASE, IFD_BIOS_MAX_MAPPED
+);
+
+/*
+ * This is how we translate physical SPI flash address space into CPU memory-mapped space. In
+ * essence this means "BIOS" region (usually starts at flash physical 0x1000 is mapped to
+ * 4G - IFD_BIOS_SIZE.
+ */
+static const struct xlate_region_device real_dev = XLATE_REGION_INIT(
+		&shadow_dev.rdev, CONFIG_IFD_BIOS_START,
+		IFD_MAPPED_SIZE, CONFIG_ROM_SIZE
+);
+
+const struct region_device *boot_device_ro(void)
+{
+	return &real_dev.rdev;
+}
+
+static int iafw_boot_region_properties(struct cbfs_props *props)
+{
+	struct region regn;
+
+	/* use fmap to locate CBFS area */
+	if (fmap_locate_area("COREBOOT", &regn))
+		return -1;
+
+	props->offset = region_offset(&regn);
+	props->size = region_sz(&regn);
+
+	printk(BIOS_DEBUG, "CBFS @ %zx size %zx\n", props->offset, props->size);
+
+	return 0;
+}
+
+/*
+ * Named cbfs_master_header_locator so that it overrides the default, but
+ * incompatible locator in cbfs.c
+ */
+const struct cbfs_locator cbfs_master_header_locator = {
+	.name = "IAFW Locator",
+	.locate = iafw_boot_region_properties,
+};