[coreboot-gerrit] Patch set updated for coreboot: intel/skylake: Remove check for Microcode loaded by ME
Martin Roth (martinroth@google.com)
gerrit at coreboot.org
Thu Jan 7 23:18:00 CET 2016
Martin Roth (martinroth at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12854
-gerrit
commit 237c8541503dd04a244ebb5e5124bcd188dd4c28
Author: Martin Roth <martinroth at google.com>
Date: Wed Jan 6 16:24:49 2016 -0700
intel/skylake: Remove check for Microcode loaded by ME
This method of reporting has been removed from the current Skylake
ME binaries so is no longer needed.
Change-Id: I774982146c19f37418f5aee29ae8883fcd3d0c8c
Signed-off-by: Martin Roth <martinroth at google.com>
---
src/soc/intel/skylake/bootblock/cpu.c | 23 +----------------------
1 file changed, 1 insertion(+), 22 deletions(-)
diff --git a/src/soc/intel/skylake/bootblock/cpu.c b/src/soc/intel/skylake/bootblock/cpu.c
index bc9d638..6fc4d92 100644
--- a/src/soc/intel/skylake/bootblock/cpu.c
+++ b/src/soc/intel/skylake/bootblock/cpu.c
@@ -171,32 +171,11 @@ static void check_for_clean_reset(void)
soft_reset();
}
-static void patch_microcode(void)
-{
- const struct microcode *patch;
- u32 current_rev;
- msr_t msr;
-
- patch = intel_microcode_find();
-
- current_rev = read_microcode_rev();
-
- /* If PRMRR/SGX is supported the FIT microcode load step will set
- * msr 0x08b with the Patch revision id one less than the id in the
- * microcode binary. The PRMRR support is indicated in the MSR
- * MTRRCAP[12]. Check for this feature and avoid reloading the
- * same microcode during early cpu initialization.
- */
- msr = rdmsr(MTRR_CAP_MSR);
- if ((msr.lo & PRMRR_SUPPORTED) && (current_rev != patch->rev - 1))
- intel_update_microcode_from_cbfs();
-}
-
static void bootblock_cpu_init(void)
{
/* Set flex ratio and reset if needed */
set_flex_ratio_to_tdp_nominal();
check_for_clean_reset();
enable_rom_caching();
- patch_microcode();
+ intel_update_microcode_from_cbfs();
}
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