[coreboot-gerrit] New patch to review for coreboot: southbridge/i82801gx: Fix sata AHCI for desktop models on ICH7
Damien Zammit (damien@zamaudio.com)
gerrit at coreboot.org
Wed Jan 13 12:29:40 CET 2016
Damien Zammit (damien at zamaudio.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12923
-gerrit
commit a0ef4a9c8ad43ae526e0c4053aee84c254c66602
Author: Damien Zammit <damien at zamaudio.com>
Date: Wed Jan 13 22:27:48 2016 +1100
southbridge/i82801gx: Fix sata AHCI for desktop models on ICH7
Tested on Intel D510MO
Controller goes into AHCI mode and works.
Change-Id: I4a3eabb5773106a0825fa2f30ee400fbfe636c7f
Signed-off-by: Damien Zammit <damien at zamaudio.com>
---
src/southbridge/intel/i82801gx/sata.c | 51 ++++++++++++++++++++---------------
1 file changed, 30 insertions(+), 21 deletions(-)
diff --git a/src/southbridge/intel/i82801gx/sata.c b/src/southbridge/intel/i82801gx/sata.c
index 29f878d..b602376 100644
--- a/src/southbridge/intel/i82801gx/sata.c
+++ b/src/southbridge/intel/i82801gx/sata.c
@@ -26,6 +26,7 @@ static void sata_init(struct device *dev)
{
u32 reg32;
u16 reg16;
+ u8 reg8;
u32 *ahci_bar;
/* Get the chip configuration */
@@ -40,6 +41,34 @@ static void sata_init(struct device *dev)
/* SATA configuration */
+ pci_write_config32(dev, 0x94,
+ pci_read_config32(dev, 0x94) | (1 << 23) | (3 << 7));
+
+ // enable clock gating for unused ports
+ pci_write_config32(dev, 0x94,
+ pci_read_config32(dev, 0x94) | (1 << 26) | (1 << 27));
+
+ if (config->sata_ahci) {
+ // set map to ahci
+ reg8 = pci_read_config8(dev, 0x90);
+ reg8 &= ~0xc3;
+ reg8 |= 0x40;
+ pci_write_config8(dev, 0x90, reg8);
+
+ // set subclass to ahci
+ reg8 = 0x6;
+ pci_write_config8(dev, 0x0a, reg8);
+ } else {
+ // set map to ide
+ reg8 = pci_read_config8(dev, 0x90);
+ reg8 &= ~0xc3;
+ pci_write_config8(dev, 0x90, reg8);
+
+ // set subclass to ide
+ reg8 = 0x1;
+ pci_write_config8(dev, 0x0a, reg8);
+ }
+
/* Enable BARs */
pci_write_config16(dev, PCI_COMMAND, 0x0007);
@@ -86,34 +115,14 @@ static void sata_init(struct device *dev)
/* Interrupt Pin is set by D31IP.PIP */
pci_write_config8(dev, INTR_LN, 0x0a);
- /* Set timings */
- pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
- IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS |
- IDE_PPE0 | IDE_IE0 | IDE_TIME0);
- pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
- IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS);
-
- /* Sync DMA */
- pci_write_config16(dev, IDE_SDMA_CNT, IDE_PSDE0);
- pci_write_config16(dev, IDE_SDMA_TIM, 0x0001);
-
- /* Set IDE I/O Configuration */
- reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0;
- pci_write_config32(dev, IDE_CONFIG, reg32);
-
- /* Set Sata Controller Mode. */
- pci_write_config8(dev, 0x90, 0x40); // 40=AHCI
-
/* In ACHI mode, bit[3:0] must always be set
* (Port status is controlled through AHCI BAR)
*/
pci_write_config8(dev, 0x92, 0x0f);
ahci_bar = (u32 *)(pci_read_config32(dev, 0x27) & ~0x3ff);
- ahci_bar[3] = config->sata_ports_implemented;
+ ahci_bar[3] = config->sata_ports_implemented; // 00 01 10 11b
- /* SATA Initialization register */
- pci_write_config32(dev, 0x94, 0x1a000180);
} else {
printk(BIOS_DEBUG, "SATA controller in plain mode.\n");
/* Set Sata Controller Mode. No Mapping(?) */
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