[coreboot-gerrit] New patch to review for coreboot: intel/skylake: Add kconfig option to skip Native SD Controller
Patrick Georgi (pgeorgi@google.com)
gerrit at coreboot.org
Thu Jan 14 11:04:50 CET 2016
Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12946
-gerrit
commit bd049155494407a3425cfa0f7fc5d6847f948342
Author: Subrata Banik <subrata.banik at intel.com>
Date: Wed Dec 2 11:42:04 2015 +0530
intel/skylake: Add kconfig option to skip Native SD Controller
Skylake Core boot should have configurable option to skip
PCH based SD 3.0 Controller from customer/reference design.
Addition to that no unused or unnecessary should list under
device view.
BUG=chrome-os-partner:48190
BRANCH=None
TEST=Build & boot Kunimitsu and LARs.
Change-Id: Ie17fd6db01e0cabcdf605017509d809b54509a0d
Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
Original-Commit-Id: 99ac17b723125822368539d0562aa35119e520fb
Original-Change-Id: I98a48f45ef442246227fd54ea021b53f824954c5
Original-Signed-off-by: Subrata Banik <subrata.banik at intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/315420
Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
src/soc/intel/skylake/Kconfig | 6 ++++++
src/soc/intel/skylake/acpi/scs.asl | 2 ++
2 files changed, 8 insertions(+)
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index 76459c9..58b828f 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -79,6 +79,12 @@ config DCACHE_RAM_SIZE
The size of the cache-as-ram region required during bootblock
and/or romstage.
+config EXCLUDE_NATIVE_SD_INTERFACE
+ bool
+ default n
+ help
+ If you set this option to n, will not use native SD controller.
+
config HEAP_SIZE
hex
default 0x80000
diff --git a/src/soc/intel/skylake/acpi/scs.asl b/src/soc/intel/skylake/acpi/scs.asl
index 52eeefe..56f27a9 100644
--- a/src/soc/intel/skylake/acpi/scs.asl
+++ b/src/soc/intel/skylake/acpi/scs.asl
@@ -70,6 +70,7 @@ Device (EMMC)
}
}
+#if !IS_ENABLED(CONFIG_EXCLUDE_NATIVE_SD_INTERFACE)
Device (SDXC)
{
Name (_ADR, 0x001E0006)
@@ -123,3 +124,4 @@ Device (SDXC)
}
}
}
+#endif
\ No newline at end of file
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