[coreboot-gerrit] Patch set updated for coreboot: skylake boards: csme: add p2sb device and hecienabled devicetree variable
Martin Roth (martinroth@google.com)
gerrit at coreboot.org
Mon Jan 18 04:25:58 CET 2016
Martin Roth (martinroth at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12977
-gerrit
commit 5ab2afadeab4aceaf17143e5b137c344beea9479
Author: Archana Patni <archana.patni at intel.com>
Date: Wed Nov 11 01:30:41 2015 +0530
skylake boards: csme: add p2sb device and hecienabled devicetree variable
The HeciEnabled decides the state of Heci1 at end of boot. Setting to 0
(default) disables Heci1 and hides the device from OS. It internally uses
the FSP Psf Unlock policy to disable the Heci1. It also adds the p2sb
device in the devicetree which is necessary for hiding and unhiding the
device.
BRANCH=none
BUG=chrome-os-partner:45618
TEST=build for kunimitsu.
CQ-DEPEND=CL:*238451
Change-Id: Ieba2ab3b4ac518cce8371069028170ba99aaf079
Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
Original-Commit-Id: cbefe9d6e9a981594534d346be67a5cd94483d05
Original-Change-Id: I8c95b5b9b28ba8441ca031f4e9ec523d913990d6
Original-Signed-off-by: Archana Patni <archana.patni at intel.com>
Original-Signed-off-by: Subramony Sesha <subramony.sesha at intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/311913
Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
src/mainboard/google/chell/devicetree.cb | 2 ++
src/mainboard/google/glados/devicetree.cb | 2 ++
src/mainboard/google/lars/devicetree.cb | 2 ++
src/mainboard/intel/kunimitsu/devicetree.cb | 2 ++
4 files changed, 8 insertions(+)
diff --git a/src/mainboard/google/chell/devicetree.cb b/src/mainboard/google/chell/devicetree.cb
index 9bd06b2..1a9f423 100644
--- a/src/mainboard/google/chell/devicetree.cb
+++ b/src/mainboard/google/chell/devicetree.cb
@@ -42,6 +42,7 @@ chip soc/intel/skylake
register "InternalGfx" = "1"
register "SkipExtGfxScan" = "1"
register "Device4Enable" = "1"
+ register "HeciEnabled" = "0"
# Enable Root port 1.
register "PcieRpEnable[0]" = "1"
@@ -126,6 +127,7 @@ chip soc/intel/skylake
device pnp 0c09.0 on end
end
end # LPC Interface
+ device pci 1f.1 on end # P2SB
device pci 1f.2 on end # Power Management Controller
device pci 1f.3 on end # Intel HDA
device pci 1f.4 on end # SMBus
diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb
index f6aaac3..5356cc1 100644
--- a/src/mainboard/google/glados/devicetree.cb
+++ b/src/mainboard/google/glados/devicetree.cb
@@ -42,6 +42,7 @@ chip soc/intel/skylake
register "InternalGfx" = "1"
register "SkipExtGfxScan" = "1"
register "Device4Enable" = "1"
+ register "HeciEnabled" = "0"
# Enable Root port 1.
register "PcieRpEnable[0]" = "1"
@@ -126,6 +127,7 @@ chip soc/intel/skylake
device pnp 0c09.0 on end
end
end # LPC Interface
+ device pci 1f.1 on end # P2SB
device pci 1f.2 on end # Power Management Controller
device pci 1f.3 on end # Intel HDA
device pci 1f.4 on end # SMBus
diff --git a/src/mainboard/google/lars/devicetree.cb b/src/mainboard/google/lars/devicetree.cb
index f08c67e..c662c99 100644
--- a/src/mainboard/google/lars/devicetree.cb
+++ b/src/mainboard/google/lars/devicetree.cb
@@ -29,6 +29,7 @@ chip soc/intel/skylake
register "InternalGfx" = "1"
register "SkipExtGfxScan" = "1"
register "Device4Enable" = "1"
+ register "HeciEnabled" = "0"
# Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch
# SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s
@@ -129,6 +130,7 @@ chip soc/intel/skylake
device pnp 0c09.0 on end
end
end # LPC Interface
+ device pci 1f.1 on end # P2SB
device pci 1f.2 on end # Power Management Controller
device pci 1f.3 on end # Intel HDA
device pci 1f.4 on end # SMBus
diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb
index 16db113..c5dc028 100644
--- a/src/mainboard/intel/kunimitsu/devicetree.cb
+++ b/src/mainboard/intel/kunimitsu/devicetree.cb
@@ -29,6 +29,7 @@ chip soc/intel/skylake
register "InternalGfx" = "1"
register "SkipExtGfxScan" = "1"
register "Device4Enable" = "1"
+ register "HeciEnabled" = "0"
# Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch
# SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s
@@ -210,6 +211,7 @@ chip soc/intel/skylake
device pnp 0c09.0 on end
end
end # LPC Interface
+ device pci 1f.1 on end # P2SB
device pci 1f.2 on end # Power Management Controller
device pci 1f.3 on end # Intel HDA
device pci 1f.4 on end # SMBus
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