[coreboot-gerrit] Patch set updated for coreboot: mb/intel/d510mo: Use native gfx init and sata AHCI by default
Damien Zammit (damien@zamaudio.com)
gerrit at coreboot.org
Mon Jan 18 07:21:57 CET 2016
Damien Zammit (damien at zamaudio.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13034
-gerrit
commit 54c460524b9e9857060dcdfe8a93900cfe00e008
Author: Damien Zammit <damien at zamaudio.com>
Date: Mon Jan 18 17:07:11 2016 +1100
mb/intel/d510mo: Use native gfx init and sata AHCI by default
Change-Id: Ic4de7a762e90b379be3814afc61467e1cd099215
Signed-off-by: Damien Zammit <damien at zamaudio.com>
---
src/mainboard/intel/d510mo/Kconfig | 2 ++
src/mainboard/intel/d510mo/devicetree.cb | 22 ++++++++++++++++------
src/mainboard/intel/d510mo/dsdt.asl | 5 ++++-
src/mainboard/intel/d510mo/mainboard.c | 11 +++--------
src/mainboard/intel/d510mo/romstage.c | 1 +
5 files changed, 26 insertions(+), 15 deletions(-)
diff --git a/src/mainboard/intel/d510mo/Kconfig b/src/mainboard/intel/d510mo/Kconfig
index 7981f92..7184665 100644
--- a/src/mainboard/intel/d510mo/Kconfig
+++ b/src/mainboard/intel/d510mo/Kconfig
@@ -23,6 +23,8 @@ config BOARD_SPECIFIC_OPTIONS
select SUPERIO_WINBOND_W83627THG
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_1024
+ select MAINBOARD_HAS_NATIVE_VGA_INIT
+ select INTEL_INT15
config MAX_CPUS
int
diff --git a/src/mainboard/intel/d510mo/devicetree.cb b/src/mainboard/intel/d510mo/devicetree.cb
index 221cc54..d2fba64 100644
--- a/src/mainboard/intel/d510mo/devicetree.cb
+++ b/src/mainboard/intel/d510mo/devicetree.cb
@@ -15,6 +15,8 @@
#
chip northbridge/intel/pineview # Northbridge
+ register "gfx.use_spread_spectrum_clock" = "0"
+
device cpu_cluster 0 on # APIC cluster
chip cpu/intel/socket_FCBGA559 # CPU
device lapic 0 on end # APIC
@@ -22,7 +24,13 @@ chip northbridge/intel/pineview # Northbridge
end
device domain 0 on # PCI domain
device pci 0.0 on end # Host Bridge
- device pci 2.0 off end # Integrated graphics controller
+ device pci 1.0 off end # PEG
+ device pci 2.0 on # Integrated graphics controller
+ subsystemid 0x8086 0x4f4d
+ end
+ device pci 2.1 on # Integrated graphics controller 2
+ subsystemid 0x8086 0x4f4d
+ end
chip southbridge/intel/i82801gx # Southbridge
register "pirqa_routing" = "0x0b"
register "pirqb_routing" = "0x0b"
@@ -32,13 +40,15 @@ chip northbridge/intel/pineview # Northbridge
register "pirqf_routing" = "0x0b"
register "pirqg_routing" = "0x0b"
register "pirqh_routing" = "0x0b"
- register "ide_legacy_combined" = "0x1"
- register "ide_enable_primary" = "0x1"
- register "ide_enable_secondary" = "0x0"
- register "sata_ahci" = "0x0"
+ register "sata_ahci" = "0x1"
+ register "sata_ports_implemented" = "0x3"
+ register "gpe0_en" = "0x20000040"
device pci 1b.0 on end # Audio
- device pci 1c.0 on end # PCIe 1
+ device pci 1c.0 on # PCIe 1
+ device pci 0.0 on # NIC
+ end
+ end
device pci 1c.1 on end # PCIe 2
device pci 1c.2 on end # PCIe 3
device pci 1c.3 on end # PCIe 4
diff --git a/src/mainboard/intel/d510mo/dsdt.asl b/src/mainboard/intel/d510mo/dsdt.asl
index c1f72f9..a7788bd 100644
--- a/src/mainboard/intel/d510mo/dsdt.asl
+++ b/src/mainboard/intel/d510mo/dsdt.asl
@@ -2,7 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
- * Copyright (C) 2015 Damien Zammit <damien at zamaudio.com>
+ * Copyright (C) 2015 Damien Zammit <damien at zamaudio.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
@@ -23,8 +23,11 @@ DefinitionBlock(
0x20090419 // OEM revision
)
{
+ #include "acpi/platform.asl"
#include <southbridge/intel/i82801gx/acpi/globalnvs.asl>
+ #include <cpu/intel/common/acpi/cpu.asl>
+
Scope (\_SB) {
Device (PCI0)
{
diff --git a/src/mainboard/intel/d510mo/mainboard.c b/src/mainboard/intel/d510mo/mainboard.c
index 3b0ef0f..4f0f32b 100644
--- a/src/mainboard/intel/d510mo/mainboard.c
+++ b/src/mainboard/intel/d510mo/mainboard.c
@@ -16,19 +16,14 @@
#include <device/device.h>
#include <device/pci_def.h>
#include <device/pci_ops.h>
-#include <drivers/intel/gma/i915.h>
#include <pc80/mc146818rtc.h>
#include <device/pci.h>
-
-const struct i915_gpu_controller_info *
-intel_gma_get_controller_info(void)
-{
- return NULL;
-}
+#include <drivers/intel/gma/int15.h>
static void mainboard_enable(device_t dev)
{
- dev->ops->init = NULL;
+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE,
+ GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_CRT, 0);
}
struct chip_operations mainboard_ops = {
diff --git a/src/mainboard/intel/d510mo/romstage.c b/src/mainboard/intel/d510mo/romstage.c
index b0bd0c0..6b4f0f6 100644
--- a/src/mainboard/intel/d510mo/romstage.c
+++ b/src/mainboard/intel/d510mo/romstage.c
@@ -50,6 +50,7 @@ static void mb_gpio_init(void)
outl(0x1ff9f7c1, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */
outl(0xe0e9e803, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */
outl(0xece9e842, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */
+ outl(0x00000000, DEFAULT_GPIOBASE + 0x18); /* GPO_BLINK */
outl(0x00002000, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */
outl(0x000000fe, DEFAULT_GPIOBASE + 0x30);
outl(0x0000007e, DEFAULT_GPIOBASE + 0x34);
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