[coreboot-gerrit] Patch set updated for coreboot: google/lars: Enable FspSkipMpInit token
Patrick Georgi (pgeorgi@google.com)
gerrit at coreboot.org
Mon Jan 18 12:42:40 CET 2016
Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12999
-gerrit
commit 737b5299541f37b6cdce1a1be6b0699e6b2140e0
Author: Barnali Sarkar <barnali.sarkar at intel.com>
Date: Fri Dec 18 15:53:08 2015 +0530
google/lars: Enable FspSkipMpInit token
MP init is already handled in coreboot, but it is also part of FSP
FSP has a implemented a provision to allow FSP to skip MP init and
let coreboot handle it.
BRANCH=none
BUG=chrome-os-partner:44805
TEST=Build and booted in Lars with SkipMpInit enabled from CB
CQ-DEPEND=CL:319353
Change-Id: Ib35d9072b883592d22466dfeb1fd45403c0479d4
Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
Original-Commit-Id: 91cf59ea7865568eca2ce242d81c4c486076d5ac
Original-Change-Id: Ibb46fc6bc7e862c9ea8bc9f9b0d508c3707282a2
Original-Signed-off-by: Barnali Sarkar <barnali.sarkar at intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/319257
Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
src/mainboard/google/lars/devicetree.cb | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mainboard/google/lars/devicetree.cb b/src/mainboard/google/lars/devicetree.cb
index 7cf2ac8..ed47820 100644
--- a/src/mainboard/google/lars/devicetree.cb
+++ b/src/mainboard/google/lars/devicetree.cb
@@ -30,6 +30,7 @@ chip soc/intel/skylake
register "SkipExtGfxScan" = "1"
register "Device4Enable" = "1"
register "HeciEnabled" = "0"
+ register "FspSkipMpInit" = "1"
# Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch
# SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s
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