[coreboot-gerrit] Patch set updated for coreboot: google/chell: Set FSP params for min assertion widths and serirq
Patrick Georgi (pgeorgi@google.com)
gerrit at coreboot.org
Mon Jan 18 12:43:54 CET 2016
Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13009
-gerrit
commit bdeef13d0c31637eb6d86321e4760bb3e5de36dc
Author: Duncan Laurie <dlaurie at chromium.org>
Date: Thu Jan 7 16:53:43 2016 -0800
google/chell: Set FSP params for min assertion widths and serirq
- Enable serial irq configuration in FSP.
- Set minimum assertion width values for FSP to configure.
- Set I2C4 voltage to 1.8V.
- Enable SaGv feature to dynamically train memory frequency.
BUG=chrome-os-partner:47688
BRANCH=none
TEST=build and boot on chell EVT
Change-Id: If6955c9ee4f08d1ebc6e98e0ba0786073919856f
Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
Original-Commit-Id: 7403149299ec2c6c66c2066a5dd8294608e71409
Original-Change-Id: Ia182396ad4eb7a283e183fce7c50c98f6d2de57c
Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/321212
Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
src/mainboard/google/chell/devicetree.cb | 33 ++++++++++++++++++++------------
1 file changed, 21 insertions(+), 12 deletions(-)
diff --git a/src/mainboard/google/chell/devicetree.cb b/src/mainboard/google/chell/devicetree.cb
index ceb1160..e401f26 100644
--- a/src/mainboard/google/chell/devicetree.cb
+++ b/src/mainboard/google/chell/devicetree.cb
@@ -44,6 +44,12 @@ chip soc/intel/skylake
register "Device4Enable" = "1"
register "HeciEnabled" = "0"
register "FspSkipMpInit" = "1"
+ register "SaGv" = "3"
+ register "SerialIrqConfigSirqEnable" = "1"
+ register "PmConfigSlpS3MinAssert" = "2" # 50ms
+ register "PmConfigSlpS4MinAssert" = "1" # 1s
+ register "PmConfigSlpSusMinAssert" = "1" # 500ms
+ register "PmConfigSlpAMinAssert" = "3" # 2s
# VR Settings Configuration for 5 Domains
#+----------------+-------+-------+-------------+-------------+-------+
@@ -144,20 +150,23 @@ chip soc/intel/skylake
register "usb3_ports[3]" = "USB3_PORT_DEFAULT" # SD
# Must leave UART0 enabled or SD/eMMC will not work as PCI
- register "SerialIoDevMode" = "{ \
- [PchSerialIoIndexI2C0] = PchSerialIoPci, \
- [PchSerialIoIndexI2C1] = PchSerialIoPci, \
- [PchSerialIoIndexI2C2] = PchSerialIoDisabled, \
- [PchSerialIoIndexI2C3] = PchSerialIoDisabled, \
- [PchSerialIoIndexI2C4] = PchSerialIoPci, \
- [PchSerialIoIndexI2C5] = PchSerialIoDisabled, \
- [PchSerialIoIndexSpi0] = PchSerialIoDisabled, \
- [PchSerialIoIndexSpi1] = PchSerialIoDisabled, \
- [PchSerialIoIndexUart0] = PchSerialIoPci, \
- [PchSerialIoIndexUart1] = PchSerialIoDisabled, \
- [PchSerialIoIndexUart2] = PchSerialIoSkipInit, \
+ register "SerialIoDevMode" = "{
+ [PchSerialIoIndexI2C0] = PchSerialIoPci,
+ [PchSerialIoIndexI2C1] = PchSerialIoPci,
+ [PchSerialIoIndexI2C2] = PchSerialIoDisabled,
+ [PchSerialIoIndexI2C3] = PchSerialIoDisabled,
+ [PchSerialIoIndexI2C4] = PchSerialIoPci,
+ [PchSerialIoIndexI2C5] = PchSerialIoDisabled,
+ [PchSerialIoIndexSpi0] = PchSerialIoDisabled,
+ [PchSerialIoIndexSpi1] = PchSerialIoDisabled,
+ [PchSerialIoIndexUart0] = PchSerialIoPci,
+ [PchSerialIoIndexUart1] = PchSerialIoDisabled,
+ [PchSerialIoIndexUart2] = PchSerialIoSkipInit,
}"
+ # I2C4 is 1.8V
+ register "SerialIoI2cVoltage[4]" = "1"
+
device cpu_cluster 0 on
device lapic 0 on end
end
More information about the coreboot-gerrit
mailing list