[coreboot-gerrit] Patch set updated for coreboot: google/lars: Enable eMMC HS400 mode
Patrick Georgi (pgeorgi@google.com)
gerrit at coreboot.org
Mon Jan 18 19:17:56 CET 2016
Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13004
-gerrit
commit 9fe228ff55fcaf48c71aabf00a77f68d22d55865
Author: david <david_wu at quantatw.com>
Date: Mon Jan 4 14:16:47 2016 +0800
google/lars: Enable eMMC HS400 mode
Kingston eMMC can now run under HS400 mode.
BUG=chrome-os-partner:48017
BRANCH=none
TEST=run consecutive boot 100 times on Lars proto Kingston SKU, and
MMC errors didn't happen.
Change-Id: I3c16db6111273fbbabbfba1c315edc780fe23525
Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
Original-Commit-Id: ac474bd7bd33f11904a27691e9eb61bdaf212c6b
Original-Change-Id: I9e47b6ba64ac94acff7673fca86fa62bfb30edd9
Original-Signed-off-by: David Wu <David_Wu at quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/320194
Original-Commit-Ready: David Wu <david_wu at quantatw.com>
Original-Tested-by: David Wu <david_wu at quantatw.com>
Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
Original-Reviewed-by: Subrata Banik <subrata.banik at intel.com>
---
src/mainboard/google/lars/devicetree.cb | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/google/lars/devicetree.cb b/src/mainboard/google/lars/devicetree.cb
index 689babb..e858eea 100644
--- a/src/mainboard/google/lars/devicetree.cb
+++ b/src/mainboard/google/lars/devicetree.cb
@@ -24,7 +24,7 @@ chip soc/intel/skylake
register "IoBufferOwnership" = "3"
register "SmbusEnable" = "1"
register "ScsEmmcEnabled" = "1"
- register "ScsEmmcHs400Enabled" = "0"
+ register "ScsEmmcHs400Enabled" = "1"
register "ScsSdCardEnabled" = "0"
register "InternalGfx" = "1"
register "SkipExtGfxScan" = "1"
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