[coreboot-gerrit] Patch set updated for coreboot: cpu/qemu-x86/romstage_entry.inc: Remove redunant cache-as-ram code
Alexandru Gagniuc (mr.nuke.me@gmail.com)
gerrit at coreboot.org
Thu Jan 21 00:53:06 CET 2016
Alexandru Gagniuc (mr.nuke.me at gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12878
-gerrit
commit 79ca66a144aaa0d0f9b897857458b04eacdf92b7
Author: Alexandru Gagniuc <mr.nuke.me at gmail.com>
Date: Fri Jan 8 22:51:21 2016 -0800
cpu/qemu-x86/romstage_entry.inc: Remove redunant cache-as-ram code
This CPU doesn't use cache-as-ram; however, since it uses a C
environment bootblock, any such setup would have to be handled in the
bootblock anyway.
Ramstage is succesfully loaded and executed with this change.
Change-Id: Ib9a70fed933ac484f8a5632b6b8f1ab9f69a9ae0
Signed-off-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
---
src/cpu/qemu-x86/romstage_entry.inc | 18 ++++--------------
1 file changed, 4 insertions(+), 14 deletions(-)
diff --git a/src/cpu/qemu-x86/romstage_entry.inc b/src/cpu/qemu-x86/romstage_entry.inc
index fcd2d3b..c2f6518 100644
--- a/src/cpu/qemu-x86/romstage_entry.inc
+++ b/src/cpu/qemu-x86/romstage_entry.inc
@@ -19,27 +19,17 @@
#include <cpu/x86/post_code.h>
#include <cbmem.h>
-#define CACHE_AS_RAM_SIZE 0x10000
-#define CACHE_AS_RAM_BASE 0xd0000
-
-#define CPU_PHYSMASK_HI (1 << (CONFIG_CPU_ADDR_BITS - 32) - 1)
+#define STACK_SIZE 0x10000
+#define STACK_BASE 0xd0000
/* Save the BIST result. */
movl %eax, %ebp
-cache_as_ram:
+qemu_x86_assembly_entry:
post_code(0x20)
- /* Clear the cache memory region. This will also fill up the cache */
- movl $CACHE_AS_RAM_BASE, %esi
- movl %esi, %edi
- movl $(CACHE_AS_RAM_SIZE >> 2), %ecx
- // movl $0x23322332, %eax
- xorl %eax, %eax
- rep stosl
- post_code(0x21)
/* Set up the stack pointer. */
- movl $(CACHE_AS_RAM_SIZE + CACHE_AS_RAM_BASE - 4), %eax
+ movl $(STACK_BASE + STACK_SIZE), %eax
movl %eax, %esp
/* Restore the BIST result. */
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