[coreboot-gerrit] New patch to review for coreboot: drivers/intel/fsp2_0: Implement FSP memory init wrapper
Andrey Petrov (andrey.petrov@intel.com)
gerrit at coreboot.org
Sun Jan 24 03:33:07 CET 2016
Andrey Petrov (andrey.petrov at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13337
-gerrit
commit 84effd95659e04f5b65f5cf9d18eac5d2cb780f7
Author: Andrey Petrov <andrey.petrov at intel.com>
Date: Thu Oct 29 13:00:54 2015 -0700
drivers/intel/fsp2_0: Implement FSP memory init wrapper
Change-Id: I7926696a74ccf9cd01898cdf502d16c93785649a
Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc at intel.com>
Signed-off-by: Andrey Petrov <andrey.petrov at intel.com>
---
src/drivers/intel/fsp2_0/Kconfig | 4 ++
src/drivers/intel/fsp2_0/Makefile.inc | 1 +
src/drivers/intel/fsp2_0/memory_init.c | 127 +++++++++++++++++++++++++++++++++
3 files changed, 132 insertions(+)
diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig
index a029965..0103921 100644
--- a/src/drivers/intel/fsp2_0/Kconfig
+++ b/src/drivers/intel/fsp2_0/Kconfig
@@ -27,6 +27,10 @@ config FSP_S_FILE
endif # ADD_FSP_BINARIES
+config FIT_CAR_ADDR
+ hex
+ default 0xfef27c00
+
# Cache As RAM region layout:
#
# +-------------+ DCACHE_RAM_BASE + DCACHE_RAM_SIZE [0xfef80000]
diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc
index b6cb7cd..763b46d 100644
--- a/src/drivers/intel/fsp2_0/Makefile.inc
+++ b/src/drivers/intel/fsp2_0/Makefile.inc
@@ -1,5 +1,6 @@
romstage-y += util.c
+romstage-y += memory_init.c
CPPFLAGS_common += -I$(src)/drivers/intel/fsp2_0/include
diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c
new file mode 100644
index 0000000..c05c286
--- /dev/null
+++ b/src/drivers/intel/fsp2_0/memory_init.c
@@ -0,0 +1,127 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corp.
+ * (Written by Andrey Petrov <andrey.petrov at intel.com> for Intel Corp.)
+ * (Written by Alexandru Gagniuc <alexandrux.gagniuc at intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <arch/io.h>
+#include <arch/cpu.h>
+#include <console/console.h>
+#include <cbmem.h>
+#include <fsp/api.h>
+#include <fsp/util.h>
+#include <string.h>
+#include <timestamp.h>
+
+#define FIT_POINTER (0x100000000ULL - 0x40)
+#define FIT_SIZE 0x400
+
+struct fsp_memory_init_params {
+ void *nvs_buffer;
+ void *rt_buffer;
+ void **hob_list;
+} __attribute__ ((__packed__));
+
+struct fsp_init_rt_common_buffer {
+ void *stack_top;
+ uint32_t boot_mode;
+ void *upd_data_rgn;
+ uint32_t bootloader_tolum_size;
+} __attribute__ ((__packed__));
+
+typedef asmlinkage enum fsp_status (*fsp_memory_init_fn)
+ (struct fsp_memory_init_params *);
+
+static void fill_console_params(struct MEMORY_INIT_UPD *memupd)
+{
+ /* TODO: Check that FSP actually respects these flags */
+ if (IS_ENABLED(CONFIG_CONSOLE_SERIAL)) {
+ memupd->SerialDebugPortDevice = CONFIG_UART_FOR_CONSOLE;
+ memupd->SerialDebugPortType = 2;
+ memupd->SerialDebugPortStrideSize = 2;
+ memupd->SerialDebugPortAddress = 0;
+ } else {
+ memupd->SerialDebugPortType = 0;
+ }
+}
+
+__attribute__((weak))
+void platform_fsp_memory_init_params_cb(struct MEMORY_INIT_UPD *memupd)
+{
+ printk(BIOS_DEBUG, "WEAK: %s called\n", __func__);
+}
+
+static enum fsp_status do_fsp_memory_init(struct fsp_header *hdr)
+{
+ enum fsp_status status;
+ fsp_memory_init_fn fsp_raminit;
+ struct fsp_memory_init_params raminit_params;
+ struct fsp_init_rt_common_buffer rt_buffer;
+ void *hob_list_ptr;
+ struct MEMORY_INIT_UPD raminit_upd;
+ struct UPD_DATA_REGION *upd_region;
+
+ post_code(0x34);
+ upd_region = (void*)(hdr->cfg_region_offset + hdr->image_base);
+ memcpy(&raminit_upd, upd_region, sizeof(raminit_upd));
+
+ /* Zero fill RT Buffer data and start populating fields. */
+ memset(&rt_buffer, 0, sizeof(rt_buffer));
+
+ rt_buffer.upd_data_rgn = &raminit_upd;
+ rt_buffer.bootloader_tolum_size = cbmem_overhead_size();
+
+ /* Get any board specific changes */
+ raminit_params.nvs_buffer = NULL;
+ raminit_params.rt_buffer = &rt_buffer;
+ raminit_params.hob_list = &hob_list_ptr;
+
+ /* Update the UPD data */
+ raminit_upd.GpioPadInitTablePtr = NULL;
+ fill_console_params(&raminit_upd);
+ platform_fsp_memory_init_params_cb(&raminit_upd);
+
+ /* Call FspMemoryInit */
+ fsp_raminit = (void *)(hdr->image_base + hdr->memory_init_entry_offset);
+ printk(BIOS_DEBUG, "Calling FspMemoryInit: 0x%p\n", fsp_memory_init);
+ printk(BIOS_SPEW, "\t%p: nvs_buffer\n", raminit_params.nvs_buffer);
+ printk(BIOS_SPEW, "\t%p: rt_buffer\n", raminit_params.rt_buffer);
+ printk(BIOS_SPEW, "\t%p: hob_list\n", raminit_params.hob_list);
+
+ timestamp_add_now(TS_FSP_MEMORY_INIT_START);
+ status = fsp_raminit(&raminit_params);
+ post_code(0x37);
+ timestamp_add_now(TS_FSP_MEMORY_INIT_END);
+
+ printk(BIOS_DEBUG, "FspMemoryInit returned 0x%08x\n", status);
+
+ return status;
+}
+
+/*
+ * Relocate FIT table to FSP-M's stack/data space
+ *
+ * FSP-M expects to find FIT entries at some address hardcoded in FSP.
+ */
+static void relocate_fit(void)
+{
+ uint32_t fit_loc = read32((void *)FIT_POINTER);
+ memcpy((void*)CONFIG_FIT_CAR_ADDR, (void*)fit_loc, FIT_SIZE);
+}
+
+enum fsp_status fsp_memory_init(void)
+{
+ struct fsp_header hdr;
+
+ if (fsp_load_binary(&hdr, "blobs/fsp-m.bin") != CB_SUCCESS)
+ return FSP_NOT_FOUND;
+ relocate_fit();
+ return do_fsp_memory_init(&hdr);
+}
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