[coreboot-gerrit] New patch to review for coreboot: soc/apollolake: Adjust CAR addresses for new FSP memory layout
Andrey Petrov (andrey.petrov@intel.com)
gerrit at coreboot.org
Sun Jan 24 03:34:09 CET 2016
Andrey Petrov (andrey.petrov at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13398
-gerrit
commit 942211b6179dc1bb3e15afa60d6246c8476610c7
Author: Alexandru Gagniuc <alexandrux.gagniuc at intel.com>
Date: Wed Jan 13 14:11:11 2016 -0800
soc/apollolake: Adjust CAR addresses for new FSP memory layout
The FSP memory layout changed, and things need to be shuffled around
a bit, as well as doubling the size of the CAR region.
Change-Id: I14cbcf5141eea9a7a69c8c1628aac701223c04e8
Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc at intel.com>
---
src/soc/intel/apollolake/Kconfig | 18 +++++-------------
1 file changed, 5 insertions(+), 13 deletions(-)
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index eb59ba5..c619e56 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -56,7 +56,7 @@ config DCACHE_RAM_BASE
config DCACHE_RAM_SIZE
hex "Length in bytes of cache-as-RAM"
- default 0x80000
+ default 0x100000
help
The size of the cache-as-ram region required during bootblock
and/or romstage.
@@ -66,21 +66,13 @@ config DCACHE_RAM_BOOTBLOCK_STACK_SIZE
default 0x800
help
The amount of anticipated stack usage from the bootblock during
- pre-romstage initialization..
+ pre-romstage initialization.
-config IFD_BIOS_START
+config ROMSTAGE_CAR_ADDR
hex
- default 0x1000
+ default 0xfef2e000
help
- The starting address of flash region 1 (BIOS), as declared in the
- firmware descriptor. This can be obtained via 'ifdtool -d'.
-
-config IFD_BIOS_END
- hex
- default ROM_SIZE
- help
- The ending address of flash region 1 (BIOS), as declared in the
- firmware descriptor. This can be obtained via 'ifdtool -d'.
+ The base address (in CAR) where romstage should be linked
config CPU_ADDR_BITS
int
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