[coreboot-gerrit] Patch set updated for coreboot: mb/gigabyte/ga-g41m-es2l: Tidy up
Damien Zammit (damien@zamaudio.com)
gerrit at coreboot.org
Mon Jan 25 03:17:13 CET 2016
Damien Zammit (damien at zamaudio.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13129
-gerrit
commit 62b1b528aac71e1f09f84dee3401d47866a4ceb1
Author: Damien Zammit <damien at zamaudio.com>
Date: Fri Jan 22 19:08:57 2016 +1100
mb/gigabyte/ga-g41m-es2l: Tidy up
- Move MMCONF base address to 0xe0000000
- Remove unnecessary copy-pasted c-states
- Remove PMBASE settings in romstage.c
Change-Id: I3873d92069cc1d113a8092d609d1768ff45cbd45
Signed-off-by: Damien Zammit <damien at zamaudio.com>
---
src/mainboard/gigabyte/ga-g41m-es2l/Kconfig | 2 +-
src/mainboard/gigabyte/ga-g41m-es2l/cstates.c | 13 +------------
src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb | 3 ---
src/mainboard/gigabyte/ga-g41m-es2l/romstage.c | 19 ++-----------------
4 files changed, 4 insertions(+), 33 deletions(-)
diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig b/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig
index 1892b37..1234569 100644
--- a/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig
+++ b/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig
@@ -30,7 +30,7 @@ config BOARD_SPECIFIC_OPTIONS
config MMCONF_BASE_ADDRESS
hex
- default 0xc0000000
+ default 0xe0000000
config MAINBOARD_DIR
string
diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/cstates.c b/src/mainboard/gigabyte/ga-g41m-es2l/cstates.c
index dbac2ed..4d9f4ab 100644
--- a/src/mainboard/gigabyte/ga-g41m-es2l/cstates.c
+++ b/src/mainboard/gigabyte/ga-g41m-es2l/cstates.c
@@ -17,18 +17,7 @@
#include <device/device.h>
#include <southbridge/intel/i82801gx/i82801gx.h>
-static acpi_cstate_t cst_entries[] = {
- {
- /* acpi C1 / cpu C1 */
- 1, 0x01, 1000,
- { ACPI_ADDRESS_SPACE_FIXED, 1, 2, { 1 }, 0, 0 }
- },
- {
- /* acpi C2 / cpu C2 */
- 2, 0x01, 500,
- { ACPI_ADDRESS_SPACE_FIXED, 1, 2, { 1 }, 0x10, 0 }
- },
-};
+static acpi_cstate_t cst_entries[] = {};
int get_cst_entries(acpi_cstate_t **entries)
{
diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb
index e6b691c..3965538 100644
--- a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb
+++ b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb
@@ -21,9 +21,6 @@ chip northbridge/intel/x4x # Northbridge
end
chip cpu/intel/model_1067x # CPU
device lapic 0xACAC off end
- register "slfm" = "1"
- register "c5" = "1"
- register "c6" = "1"
end
end
device domain 0 on # PCI domain
diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c
index 6bae128..08a7a98 100644
--- a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c
+++ b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c
@@ -58,21 +58,6 @@ static void mb_gpio_init(void)
outl(0x000000f0, DEFAULT_GPIOBASE + 0x34);
outl(0x00000083, DEFAULT_GPIOBASE + 0x38);
- /* Set default power management registers */
- pci_write_config32(dev, PMBASE, DEFAULT_PMBASE | 1);
- outw(0x0011, DEFAULT_PMBASE + 0x00);
- outw(0x0120, DEFAULT_PMBASE + 0x02);
- outl(0x00001c01, DEFAULT_PMBASE + 0x04);
- outl(0x00bb29d2, DEFAULT_PMBASE + 0x08);
- outl(0x000000a0, DEFAULT_PMBASE + 0x10);
- outl(0xc5000000, DEFAULT_PMBASE + 0x28);
- outl(0x00000040, DEFAULT_PMBASE + 0x2c);
- outw(0x13e0, DEFAULT_PMBASE + 0x44);
- outw(0x003f, DEFAULT_PMBASE + 0x60);
- outw(0x0800, DEFAULT_PMBASE + 0x68);
- outw(0x0008, DEFAULT_PMBASE + 0x6a);
- outw(0x003f, DEFAULT_PMBASE + 0x72);
-
/* Set default GPIOs on superio */
ite_reg_write(GPIO_DEV, 0x25, 0x00);
ite_reg_write(GPIO_DEV, 0x26, 0xc7);
@@ -137,8 +122,8 @@ void main(unsigned long bist)
// ch0 ch1
const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 };
- /* Disable watchdog timer and route port 80 to LPC */
- RCBA32(0x3410) = (RCBA32(0x3410) | 0x20);// & ~0x4;
+ /* Disable watchdog timer */
+ RCBA32(0x3410) = RCBA32(0x3410) | 0x20;
/* Set southbridge and Super I/O GPIOs. */
mb_gpio_init();
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