[coreboot-gerrit] New patch to review for coreboot: x86 Docs: Add bootblock support
Leroy P Leahy (leroy.p.leahy@intel.com)
gerrit at coreboot.org
Tue Jan 26 01:34:40 CET 2016
Leroy P Leahy (leroy.p.leahy at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13441
-gerrit
commit 220c1fc853f53a5b7dd00212dc3f95250745e6a8
Author: Lee Leahy <leroy.p.leahy at intel.com>
Date: Thu Jan 7 11:16:25 2016 -0800
x86 Docs: Add bootblock support
Document what is involved with adding the bootblock support.
BRANCH=none
BUG=None
TEST=None
Change-Id: I6c8cc38e1b9346b4962588b33ca5e4ab8eac24c3
Signed-off-by: Lee Leahy <leroy.p.leahy at intel.com>
---
Documentation/x86Development.html | 1 +
Documentation/x86SoC.html | 83 +++++++++++++++++++++++++++++++++++++++
2 files changed, 84 insertions(+)
diff --git a/Documentation/x86Development.html b/Documentation/x86Development.html
index 3bd18f0..8cd697f 100644
--- a/Documentation/x86Development.html
+++ b/Documentation/x86Development.html
@@ -43,6 +43,7 @@
</li>
<li>Get result to start <a target="_blank" href="x86SoC.html#Descriptor">booting</a></li>
<li><a target="_blank" href="x86SoC.html#EarlyDebug">Early Debug</a></li>
+ <li>Implement and debug the <a target="_blank" href="x86SoC.html#Bootblock">bootblock</a> code</li>
</ol>
diff --git a/Documentation/x86SoC.html b/Documentation/x86SoC.html
index 758f913..5eab50d 100644
--- a/Documentation/x86SoC.html
+++ b/Documentation/x86SoC.html
@@ -17,6 +17,7 @@
<li>SoC <a href="#RequiredFiles">Required Files</a></li>
<li><a href="#Descriptor">Start Booting</a></li>
<li><a href="#EarlyDebug">Early Debug</a></li>
+ <li><a href="#BootBlock">Bootblock</a></li>
</ol>
@@ -98,6 +99,88 @@ mv build/coreboot.rom.new build/coreboot.rom
<hr>
+<h1><a name="Bootblock">Bootblock</a></h1>
+<p>
+ Implement the bootblock using the following steps:
+</p>
+<ol>
+ <li>Create the directory as src/soc/<Vendor>/<Chip Family>/bootblock</li>
+ <li>Add the timestamp.inc file which initializes the floating point registers and saves
+ the initial timestamp.
+ </li>
+ <li>Add the bootblock.c file which:
+ <ol type="A">
+ <li>Enables memory-mapped PCI config access</li>
+ <li>Updates the microcode by calling intel_update_microcode_from_cbfs</li>
+ <li>Enable ROM caching</li>
+ </ol>
+ </li>
+ <li>Edit the src/soc/<Vendor>/<Chip Family>/Kconfig file
+ <ol type="A">
+ <li>Add the BOOTBLOCK_CPU_INIT value to point to the bootblock.c file</li>
+ <li>Add the CHIPSET_BOOTBLOCK_INCLUDE value to point to the timestamp.inc file</li>
+ </ol>
+ </li>
+ <li>Edit the src/soc/<Vendor>/<Chip Family>/Makefile.inc file
+ <ol type="A">
+ <li>Add the bootblock subdirectory</li>
+ </ol>
+ </li>
+ <li>Edit the src/soc/<Vendor>/<Chip Family>/memmap.c file
+ <ol type="A">
+ <li>Add the fsp/memmap.h include file</li>
+ <li>Add the mmap_region_granularity routine</li>
+ </ol>
+ </li>
+ <li>Add the necessary .h files to define the necessary values and structures</li>
+ <li>When successful port 0x80 will output the following values:
+ <ol type="A">
+ <li>0x01: <a target="_blank" href="https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/chromeos-2015.07/src/include/console/post_codes.h#49">POST_RESET_VECTOR_CORRECT</a>
+ - Bootblock reached the
+ <a target="_blank" href="https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/chromeos-2015.07/src/cpu/x86/16bit/entry16.inc#35">reset vector</a>
+ </li>
+ <li>0x10: <a target="_blank" href="https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/chromeos-2015.07/src/include/console/post_codes.h#57">POST_ENTER_PROTECTED_MODE</a>
+ - Bootblock reached
+ <a target="_blank" href="https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/chromeos-2015.07/src/cpu/x86/32bit/entry32.inc#55">32-bit mode</a>
+ </li>
+ <li>0x10 - Verstage/romstage reached 32-bit mode</li>
+ </ol>
+ </li>
+</ol>
+
+<p>
+ <b>Build Note:</b> The following files are included into the default bootblock image:
+</p>
+<ul>
+ <li><a target="_blank" href="https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/chromeos-2015.07/src/arch/x86/bootblock.S">src/arch/x86/bootblock.S</a></li>
+ <li><a target="_blank" href="https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/chromeos-2015.07/src/arch/x86/prologue.inc">src/arch/x86/prologue.inc</a></li>
+ <li><a target="_blank" href="https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/chromeos-2015.07/src/cpu/x86/16bit/reset16.inc">src/cpu/x86/16bit/reset16.inc</a></li>
+ <li><a target="_blank" href="https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/chromeos-2015.07/src/cpu/x86/16bit/entry16.inc">src/cpu/x86/16bit/entry16.inc</a></li>
+ <li><a target="_blank" href="https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/chromeos-2015.07/src/cpu/x86/32bit/entry32.inc">src/cpu/x86/32bit/entry32.inc</a></li>
+ <li><a target="_blank" href="https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/chromeos-2015.07/src/arch/x86/id.inc">src/arch/x86/id.inc</a></li>
+ <li><a target="_blank" href="https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/chromeos-2015.07/src/cpu/intel/fit/fit.inc">src/cpu/intel/fit/fit.inc</a></li>
+ <li>The code in
+ <a target="_blank" href="https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/chromeos-2015.07/src/arch/x86/bootblock.S">src/arch/x86/bootblock.S</a>
+ includes src/soc/<Vendor>/<Chip Family>/bootblock/timestamp.inc using the
+ CONFIG_CHIPSET_BOOTBLOCK_INCLUDE value set above
+ </li>
+ <li><a target="_blank" href="https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/chromeos-2015.07/src/cpu/x86/sse_enable.inc">src/cpu/x86/sse_enable.inc</a></li>
+ <li>The code in
+ <a target="_blank" href="https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/chromeos-2015.07/src/arch/x86/Makefile.inc#71">src/arch/x86/Makefile.inc</a>
+ invokes the ROMCC tool to convert the following "C" code into assembler as bootblock.inc:
+ <ul>
+ <li><a target="_blank" href="https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/chromeos-2015.07/src/arch/x86/include/arch/bootblock_common.h">src/arch/x86/include/arch/bootblock_common.h</a></li>
+ <li><a target="_blank" href="https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/chromeos-2015.07/src/cpu/x86/lapic/boot_cpu.c">src/cpu/x86/lapic/boot_cpu.c</a></li>
+ <li>The CONFIG_BOOTBLOCK_CPU_INIT value set above points to the code in
+ src/soc/<Vendor>/<Chip Family>/bootblockbootblock.c
+ </li>
+ </ul>
+ </li>
+ <li><a target="_blank" href="https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/chromeos-2015.07/src/arch/x86/walkcbfs.S">src/arch/x86/walkcbfs.S</a></li>
+</ul>
+
+
+<hr>
<p>Modified: 24 January 2016</p>
</body>
</html>
\ No newline at end of file
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