[coreboot-gerrit] Patch set updated for coreboot: soc/apollolake: Add cbmem_top() implementation
Alexandru Gagniuc (mr.nuke.me@gmail.com)
gerrit at coreboot.org
Tue Jan 26 18:05:45 CET 2016
Alexandru Gagniuc (mr.nuke.me at gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13329
-gerrit
commit c847af56f55393f94f40c45da81455fb3b00ecf6
Author: Andrey Petrov <andrey.petrov at intel.com>
Date: Mon Nov 2 13:47:43 2015 -0800
soc/apollolake: Add cbmem_top() implementation
Change-Id: Ibae9f43192f0e498e91ff8a51bd7d1e9a5b31350
Signed-off-by: Andrey Petrov <andrey.petrov at intel.com>
---
src/soc/intel/apollolake/Makefile.inc | 2 ++
src/soc/intel/apollolake/memmap.c | 27 +++++++++++++++++++++++++++
src/soc/intel/apollolake/placeholders.c | 5 -----
3 files changed, 29 insertions(+), 5 deletions(-)
diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc
index e57342a..7cddf5a 100644
--- a/src/soc/intel/apollolake/Makefile.inc
+++ b/src/soc/intel/apollolake/Makefile.inc
@@ -18,12 +18,14 @@ bootblock-y += uart_early.c
cpu_incs-y += $(src)/soc/intel/apollolake/romstage/entry.inc
romstage-y += cpu.c
romstage-y += gpio.c
+romstage-y += memmap.c
romstage-y += mmap_boot.c
romstage-y += romstage/romstage.c
romstage-y += uart_early.c
ramstage-y += cpu.c
ramstage-y += gpio.c
+ramstage-y += memmap.c
ramstage-y += mmap_boot.c
ramstage-y += uart.c
diff --git a/src/soc/intel/apollolake/memmap.c b/src/soc/intel/apollolake/memmap.c
new file mode 100644
index 0000000..7de6217
--- /dev/null
+++ b/src/soc/intel/apollolake/memmap.c
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corp.
+ * (Written by Andrey Petrov <andrey.petrov at intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#define TSEG 0xb8
+
+#define __SIMPLE_DEVICE__
+#include <arch/io.h>
+#include <cbmem.h>
+
+static uintptr_t smm_region_start(void)
+{
+ return pci_read_config32(PCI_DEV(0, 0, 0), TSEG) & (~1);
+}
+
+void *cbmem_top(void)
+{
+ return (void *)smm_region_start();
+}
diff --git a/src/soc/intel/apollolake/placeholders.c b/src/soc/intel/apollolake/placeholders.c
index cf0fe36..fc62d80 100644
--- a/src/soc/intel/apollolake/placeholders.c
+++ b/src/soc/intel/apollolake/placeholders.c
@@ -1,11 +1,6 @@
#include <cbmem.h>
#include <cpu/x86/smm.h>
-void *cbmem_top(void)
-{
- return NULL;
-}
-
void southbridge_smi_set_eos(void)
{
}
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