[coreboot-gerrit] Patch set updated for coreboot: drivers/intel/fsp1_1: Remove extra include references
Leroy P Leahy (leroy.p.leahy@intel.com)
gerrit at coreboot.org
Wed Jan 27 03:12:01 CET 2016
Leroy P Leahy (leroy.p.leahy at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13436
-gerrit
commit 23532466754582109368c4c64dda96c1e00f0021
Author: Lee Leahy <lpleahyjr at gmail.com>
Date: Fri Jan 1 18:09:50 2016 -0800
drivers/intel/fsp1_1: Remove extra include references
Remove include references to the soc include directory which are not
required to build the FSP driver. Move the definition of
fill_power_state into soc/pm.h to ensure it is still available.
TEST=Build and run on Galileo
Change-Id: Ie519b3a8da8c36b47da512d3811796eab62ce208
Signed-off-by: Lee Leahy <leroy.p.leahy at intel.com>
---
src/drivers/intel/fsp1_1/raminit.c | 5 ++---
src/drivers/intel/fsp1_1/romstage.c | 6 ++----
src/soc/intel/braswell/include/soc/pm.h | 2 ++
src/soc/intel/braswell/include/soc/romstage.h | 1 -
src/soc/intel/skylake/include/soc/pm.h | 2 ++
src/soc/intel/skylake/include/soc/romstage.h | 2 --
6 files changed, 8 insertions(+), 10 deletions(-)
diff --git a/src/drivers/intel/fsp1_1/raminit.c b/src/drivers/intel/fsp1_1/raminit.c
index 2ba77e3..e505b93 100644
--- a/src/drivers/intel/fsp1_1/raminit.c
+++ b/src/drivers/intel/fsp1_1/raminit.c
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2014-2015 Intel Corporation
+ * Copyright (C) 2014-2016 Intel Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -16,12 +16,11 @@
#include <cbmem.h>
#include <console/console.h>
#include <fsp/memmap.h>
+#include <fsp/romstage.h>
#include <fsp/util.h>
#include <lib.h> /* hexdump */
#include <reset.h>
#include <soc/intel/common/mma.h>
-#include <soc/pei_data.h>
-#include <soc/romstage.h>
#include <string.h>
#include <timestamp.h>
#include <bootmode.h>
diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c
index 16db4df..0353c0c 100644
--- a/src/drivers/intel/fsp1_1/romstage.c
+++ b/src/drivers/intel/fsp1_1/romstage.c
@@ -2,7 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Google Inc.
- * Copyright (C) 2015 Intel Corporation.
+ * Copyright (C) 2015-2016 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -28,6 +28,7 @@
#include <ec/google/chromeec/ec.h>
#include <ec/google/chromeec/ec_commands.h>
#include <elog.h>
+#include <fsp/romstage.h>
#include <fsp/util.h>
#include <memory_info.h>
#include <reset.h>
@@ -35,10 +36,7 @@
#include <smbios.h>
#include <soc/intel/common/mrc_cache.h>
#include <soc/intel/common/util.h>
-#include <soc/pei_wrapper.h>
#include <soc/pm.h>
-#include <soc/romstage.h>
-#include <soc/spi.h>
#include <stage_cache.h>
#include <timestamp.h>
#include <tpm.h>
diff --git a/src/soc/intel/braswell/include/soc/pm.h b/src/soc/intel/braswell/include/soc/pm.h
index 9708b39..79a6592 100644
--- a/src/soc/intel/braswell/include/soc/pm.h
+++ b/src/soc/intel/braswell/include/soc/pm.h
@@ -235,6 +235,8 @@ struct chipset_power_state {
int prev_sleep_state;
} __attribute__((packed));
+struct chipset_power_state *fill_power_state(void);
+
/* Power Management Utility Functions. */
uint16_t get_pmbase(void);
uint32_t clear_smi_status(void);
diff --git a/src/soc/intel/braswell/include/soc/romstage.h b/src/soc/intel/braswell/include/soc/romstage.h
index e70510b..262797d 100644
--- a/src/soc/intel/braswell/include/soc/romstage.h
+++ b/src/soc/intel/braswell/include/soc/romstage.h
@@ -33,7 +33,6 @@ void set_max_freq(void);
/* romstage_common.c functions */
void program_base_addresses(void);
-struct chipset_power_state *fill_power_state(void);
int chipset_prev_sleep_state(struct chipset_power_state *ps);
#endif /* _SOC_ROMSTAGE_H_ */
diff --git a/src/soc/intel/skylake/include/soc/pm.h b/src/soc/intel/skylake/include/soc/pm.h
index 79861e9..31cf7b4 100644
--- a/src/soc/intel/skylake/include/soc/pm.h
+++ b/src/soc/intel/skylake/include/soc/pm.h
@@ -159,6 +159,8 @@ struct chipset_power_state {
uint32_t prev_sleep_state;
} __attribute__ ((packed));
+struct chipset_power_state *fill_power_state(void);
+
/* PM1_CNT */
void enable_pm1_control(uint32_t mask);
void disable_pm1_control(uint32_t mask);
diff --git a/src/soc/intel/skylake/include/soc/romstage.h b/src/soc/intel/skylake/include/soc/romstage.h
index 5e73e1c..e65bce2 100644
--- a/src/soc/intel/skylake/include/soc/romstage.h
+++ b/src/soc/intel/skylake/include/soc/romstage.h
@@ -19,8 +19,6 @@
#include <fsp/romstage.h>
-struct chipset_power_state;
-struct chipset_power_state *fill_power_state(void);
void systemagent_early_init(void);
void pch_early_init(void);
void pch_uart_init(void);
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