[coreboot-gerrit] Patch set updated for coreboot: ec/google/chromeec/acpi :Enable DPTF charger/TSR1/TSR2 participant
Hannah Williams (hannah.williams@intel.com)
gerrit at coreboot.org
Thu Jan 28 03:19:48 CET 2016
Hannah Williams (hannah.williams at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12748
-gerrit
commit fccdb2e7aa88e22049500b9da5515b18c255f61c
Author: Freddy Paul <freddy.paul at intel.com>
Date: Fri Oct 2 19:06:57 2015 -0700
ec/google/chromeec/acpi :Enable DPTF charger/TSR1/TSR2 participant
.
TEST=Plug/Unplug AC Adapter multiple times and make sure device is
charging properly.
Original-Reviewed-on: https://chromium-review.googlesource.com/303990
Original-Reviewed-by: Jenny Tc <jenny.tc at intel.com>
Original-Reviewed-by: T.H. Lin <T.H_Lin at quantatw.com>
Original-Tested-by: T.H. Lin <T.H_Lin at quantatw.com>
Original-Tested-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy at intel.com>
Original-Reviewed-by: Divya Jyothi <divya.jyothi at intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
Original-Signed-off-by: Freddy Paul <freddy.paul at intel.com>
Change-Id: I188e80e6688d0bac5bed6dd64cd2d0feefa30d3f
Signed-off-by: Hannah Williams <hannah.williams at intel.com>
Signed-off-by: Freddy Paul <freddy.paul at intel.com>
Signed-off-by: Hannah Williams <hannah.williams at intel.com>
---
src/ec/google/chromeec/acpi/ec.asl | 6 ++++++
src/mainboard/google/cyan/acpi/dptf.asl | 29 +++++++++++++++++++++--------
2 files changed, 27 insertions(+), 8 deletions(-)
diff --git a/src/ec/google/chromeec/acpi/ec.asl b/src/ec/google/chromeec/acpi/ec.asl
index 68d5106..4eb4e17 100644
--- a/src/ec/google/chromeec/acpi/ec.asl
+++ b/src/ec/google/chromeec/acpi/ec.asl
@@ -22,7 +22,9 @@
// Mainboard specific throttle handler
External (\_TZ.THRT, MethodObj)
External (\_SB.DPTF.TEVT, MethodObj)
+#ifdef DPTF_ENABLE_CHARGER
External (\_SB.DPTF.TCHG, DeviceObj)
+#endif
Device (EC0)
{
@@ -170,10 +172,12 @@ Device (EC0)
Store ("EC: AC CONNECTED", Debug)
Store (ACEX, \PWRS)
Notify (AC, 0x80)
+#ifdef DPTF_ENABLE_CHARGER
If (CondRefOf (\_SB.DPTF.TCHG)) {
\_SB.DPTF.TCHG.SPPC (\_SB.DPTF.TCHG.PPPC ())
Notify (\_SB.DPTF.TCHG, 0x80)
}
+#endif
\PNOT ()
}
@@ -183,9 +187,11 @@ Device (EC0)
Store ("EC: AC DISCONNECTED", Debug)
Store (ACEX, \PWRS)
Notify (AC, 0x80)
+#ifdef DPTF_ENABLE_CHARGER
If (CondRefOf (\_SB.DPTF.TCHG)) {
Notify (\_SB.DPTF.TCHG, 0x80)
}
+#endif
\PNOT ()
}
diff --git a/src/mainboard/google/cyan/acpi/dptf.asl b/src/mainboard/google/cyan/acpi/dptf.asl
index 95b6951..ffa8886 100755
--- a/src/mainboard/google/cyan/acpi/dptf.asl
+++ b/src/mainboard/google/cyan/acpi/dptf.asl
@@ -16,18 +16,20 @@
#define DPTF_TSR0_SENSOR_ID 0
#define DPTF_TSR0_SENSOR_NAME "TMP432_Internal"
-#define DPTF_TSR0_PASSIVE 49
-#define DPTF_TSR0_CRITICAL 75
+#define DPTF_TSR0_PASSIVE 48
+#define DPTF_TSR0_CRITICAL 70
+
#define DPTF_TSR1_SENSOR_ID 1
#define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top"
-#define DPTF_TSR1_PASSIVE 65
-#define DPTF_TSR1_CRITICAL 85
+#define DPTF_TSR1_PASSIVE 60
+#define DPTF_TSR1_CRITICAL 70
#define DPTF_TSR2_SENSOR_ID 2
#define DPTF_TSR2_SENSOR_NAME "TMP432_CPU_bottom"
-#define DPTF_TSR2_PASSIVE 49
-#define DPTF_TSR2_CRITICAL 75
+#define DPTF_TSR2_PASSIVE 55
+#define DPTF_TSR2_CRITICAL 70
+
#define DPTF_ENABLE_CHARGER
@@ -48,7 +50,18 @@ Name (DTRT, Package () {
Package () { \_SB.PCI0.B0DB, \_SB.PCI0.B0DB, 100, 50, 0, 0, 0, 0 },
/* CPU Effect on Temp Sensor 0 */
- Package () { \_SB.PCI0.B0DB, \_SB.DPTF.TSR0, 100, 100, 0, 0, 0, 0 },
+ Package () { \_SB.PCI0.B0DB, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 },
+
+#ifdef DPTF_ENABLE_CHARGER
+ /* Charger Effect on Temp Sensor 1 */
+ Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 200, 600, 0, 0, 0, 0 },
+#endif
+
+ /* CPU Effect on Temp Sensor 1 */
+ Package () { \_SB.PCI0.B0DB, \_SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 },
+
+ /* CPU Effect on Temp Sensor 2 */
+ Package () { \_SB.PCI0.B0DB, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 },
})
Name (MPPC, Package ()
@@ -56,7 +69,7 @@ Name (MPPC, Package ()
0x2, /* Revision */
Package () { /* Power Limit 1 */
0, /* PowerLimitIndex, 0 for Power Limit 1 */
- 2000, /* PowerLimitMinimum */
+ 1600, /* PowerLimitMinimum */
6200, /* PowerLimitMaximum */
1000, /* TimeWindowMinimum */
1000, /* TimeWindowMaximum */
More information about the coreboot-gerrit
mailing list