[coreboot-gerrit] Patch merged into coreboot/master: intel/skylake: Implement native Cache-as-RAM (CAR)
gerrit at coreboot.org
gerrit at coreboot.org
Fri Jan 29 16:56:04 CET 2016
the following patch was just integrated into master:
commit fbdc71941454cd4f6dbaebb3e38d27d11ab256ea
Author: Subrata Banik <subrata.banik at intel.com>
Date: Tue Jan 19 19:19:15 2016 +0530
intel/skylake: Implement native Cache-as-RAM (CAR)
Now coreboot should do BIOS CAR setup along with NEM
mode setup.
This patch also provides a mechanism to use 16MB code caching
benefit although LLC still limited to 1M/1.5M based
on SOC LLC limit.
Here with unlimited cache line gets replaced. Now we could use
unlimited cache size along with well defined data size
[pg: updated to current upstream #defines]
BUG=chrome-os-partner:48412
BRANCH=glados
TEST=Builds and Boots on FAB4 SKU2/3.
Signed-off-by: Subrata Banik <subrata.banik at intel.com>
Signed-off-by: pchandri <preetham.chandrian at intel.com>
Signed-off-by: Dhaval Sharma <dhaval.v.sharma at intel.com>
Change-Id: I96a9cf3a6e41cae9619c683dca28ad31dcaa2536
Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
Original-Commit-Id: 2ec51f15c874ad2f1f4fad52fa8deced7b27a24b
Original-Change-Id: Id62c15799d98bc27b5e558adfa7c7b3468aa153a
Original-Reviewed-on: https://chromium-review.googlesource.com/320855
Original-Commit-Ready: Subrata Banik <subrata.banik at intel.com>
Original-Tested-by: Subrata Banik <subrata.banik at intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
Reviewed-on: https://review.coreboot.org/13138
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth at google.com>
See https://review.coreboot.org/13138 for details.
-gerrit
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