[coreboot-gerrit] Patch set updated for coreboot: Northbridge/i945 clean fsbclk function
HAOUAS Elyes (ehaouas@noos.fr)
gerrit at coreboot.org
Wed Jul 6 15:53:00 CEST 2016
HAOUAS Elyes (ehaouas at noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14456
-gerrit
commit 90d32f35c1787e65d49c98b3d6e8d93835903c7c
Author: Elyes HAOUAS <ehaouas at noos.fr>
Date: Thu Apr 21 22:14:51 2016 +0200
Northbridge/i945 clean fsbclk function
Merge I945GM and I945GC cases in to the same fsbclk function.
Change-Id: I7dcdc641d647b45a086098a316043883d0b3fefb
Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
src/northbridge/intel/i945/raminit.c | 32 ++++++++++++++++----------------
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c
index 59a31de..14edf2b 100644
--- a/src/northbridge/intel/i945/raminit.c
+++ b/src/northbridge/intel/i945/raminit.c
@@ -119,29 +119,29 @@ static int memclk(void)
return -1;
}
-#if CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM
-static u16 fsbclk(void)
-{
- switch (MCHBAR32(CLKCFG) & 7) {
- case 0: return 400;
- case 1: return 533;
- case 3: return 667;
- default: printk(BIOS_DEBUG, "fsbclk: unknown register value %x\n", MCHBAR32(CLKCFG) & 7);
- }
- return 0xffff;
-}
-#elif CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC
static u16 fsbclk(void)
{
switch (MCHBAR32(CLKCFG) & 7) {
- case 0: return 1066;
- case 1: return 533;
- case 2: return 800;
+ /* should be equal to MSR_FSB_FREQ ? */
+ case 0:
+ #if CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM
+ return 400;
+ #elif CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC
+ return 1066; // 266.67 MHz should be utilized if
+ // performing calculation with System Bus Speed
+ #endif
+ case 1: return 533; // 133.33 MHz
+ case 2: return 800; // 200 MHz
+ case 3: return 667; // 166.67 MHz
+ case 4: return 1333; // 333.33 MHz
+ case 5: return 400; // 100 MHz
+ case 6: return 1600; // 400 MHz
+ case 7: return 333; // 83 MHz
+
default: printk(BIOS_DEBUG, "fsbclk: unknown register value %x\n", MCHBAR32(CLKCFG) & 7);
}
return 0xffff;
}
-#endif
static int sdram_capabilities_max_supported_memory_frequency(void)
{
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