[coreboot-gerrit] Patch set updated for coreboot: soc/intel/apollolake: Add handler for SCI
Shaunak Saha (shaunak.saha@intel.com)
gerrit at coreboot.org
Mon Jul 11 08:31:58 CEST 2016
Shaunak Saha (shaunak.saha at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15578
-gerrit
commit d280e5d22e1161595cedc53cf698a2199b2478cf
Author: Shaunak Saha <shaunak.saha at intel.com>
Date: Thu Jul 7 14:48:21 2016 -0700
soc/intel/apollolake: Add handler for SCI
This patch adds the handler to enable bit for gpio_tier1_sci_en.
gpio_tier1_sci_en enables the setting of the GPIO_TIER1_SCI_STS
bit to generate a wake event and/or an SCI or SMI#. We are setting
the bit for gpio_tier1_sci_en from the ASL code as OS clears this bit
if set from BIOS. As per ACPI spec _GPE is defined as the Named
Object that evaluates to either an integer or a package. If _GPE
evaluates to an integer, the value is the bit assignment of the SCI
interrupt within the GPEx_STS register of a GPE block described in
the FADT that the embedded controller will trigger. FADT right now
has no mechanism to acheive the same.
Change-Id: I1e1bd3f5c89a5e6bea2d1858569a9d30e6da78fe
Signed-off-by: Shaunak Saha <shaunak.saha at intel.com>
---
src/soc/intel/apollolake/acpi/gpio.asl | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/src/soc/intel/apollolake/acpi/gpio.asl b/src/soc/intel/apollolake/acpi/gpio.asl
index 4bf0442..7d115ed 100644
--- a/src/soc/intel/apollolake/acpi/gpio.asl
+++ b/src/soc/intel/apollolake/acpi/gpio.asl
@@ -142,3 +142,9 @@ scope (\_SB) {
}
}
}
+
+Scope(\_GPE)
+{
+ /* Dummy method for the Tier 1 GPIO SCI enable bit */
+ Method(_L0F, 0) {}
+}
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