[coreboot-gerrit] Patch set updated for coreboot: soc/intel/skylake: provide poweroff() implementation
Aaron Durbin (adurbin@chromium.org)
gerrit at coreboot.org
Thu Jul 14 21:13:41 CEST 2016
Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15688
-gerrit
commit 8d3cc60435f6f73d5ad89646a3e3ab414fd1c8b7
Author: Aaron Durbin <adurbin at chromium.org>
Date: Thu Jul 14 00:56:58 2016 -0500
soc/intel/skylake: provide poweroff() implementation
Implement poweroff() by putting the chipset into ACPI S5 state.
BUG=chrome-os-partner:54977
Change-Id: I9288dcee13347a8aa3f822ca3d75148ba2792859
Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
src/soc/intel/skylake/pmutil.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c
index 67ca9bd..0f74734 100644
--- a/src/soc/intel/skylake/pmutil.c
+++ b/src/soc/intel/skylake/pmutil.c
@@ -24,6 +24,7 @@
#include <device/pci.h>
#include <device/pci_def.h>
#include <console/console.h>
+#include <halt.h>
#include <stdlib.h>
#include <soc/gpio.h>
#include <soc/iomap.h>
@@ -430,3 +431,9 @@ uint16_t pmc_tco_regs(void)
return reg16;
}
+
+void poweroff(void)
+{
+ enable_pm1_control(SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT));
+ halt();
+}
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