[coreboot-gerrit] Patch set updated for coreboot: soc/intel/common: Add reset_prepare() for common reset
Andrey Petrov (andrey.petrov@intel.com)
gerrit at coreboot.org
Mon Jul 18 21:14:56 CEST 2016
Andrey Petrov (andrey.petrov at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15720
-gerrit
commit d697cfbab40b47158947fc52eb59340b44a7ed94
Author: Andrey Petrov <andrey.petrov at intel.com>
Date: Fri Jul 15 13:31:09 2016 -0700
soc/intel/common: Add reset_prepare() for common reset
Some Intel SoC may need preparation before reset can be properly
handled. Add callback that chip/soc code can implement.
BUG=chrome-os-partner:55055
Change-Id: I45857838e1a306dbcb9ed262b55e7db88a8944e5
Signed-off-by: Andrey Petrov <andrey.petrov at intel.com>
---
src/include/reset.h | 3 ++-
src/soc/intel/common/reset.c | 11 +++++++++++
2 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/src/include/reset.h b/src/include/reset.h
index 95ba608..67f58db 100644
--- a/src/include/reset.h
+++ b/src/include/reset.h
@@ -10,5 +10,6 @@ void soft_reset(void);
void cpu_reset(void);
/* Some Intel SoCs use a special reset that is specific to SoC */
void global_reset(void);
-
+/* Some Intel SoCs may need to prepare/wait before reset */
+void reset_prepare(void);
#endif
diff --git a/src/soc/intel/common/reset.c b/src/soc/intel/common/reset.c
index 79547c6..08f36b6 100644
--- a/src/soc/intel/common/reset.c
+++ b/src/soc/intel/common/reset.c
@@ -25,8 +25,17 @@
#define RST_CPU (1 << 2)
#define SYS_RST (1 << 1)
+#ifdef __ROMCC__
+#define WEAK
+#else
+#define WEAK __attribute__((weak))
+#endif
+
+void WEAK reset_prepare(void) { /* do nothing */ }
+
void hard_reset(void)
{
+ reset_prepare();
/* S0->S5->S0 trip. */
outb(RST_CPU | SYS_RST | FULL_RST, RST_CNT);
while (1)
@@ -35,6 +44,7 @@ void hard_reset(void)
void soft_reset(void)
{
+ reset_prepare();
/* PMC_PLTRST# asserted. */
outb(RST_CPU | SYS_RST, RST_CNT);
while (1)
@@ -43,6 +53,7 @@ void soft_reset(void)
void cpu_reset(void)
{
+ reset_prepare();
/* Sends INIT# to CPU */
outb(RST_CPU, RST_CNT);
while (1)
More information about the coreboot-gerrit
mailing list