[coreboot-gerrit] Patch set updated for coreboot: intel/amenia: Write protect GPIO relative to bank offset
Susendra Selvaraj (susendra.selvaraj@intel.com)
gerrit at coreboot.org
Wed Jul 20 11:21:06 CEST 2016
Susendra Selvaraj (susendra.selvaraj at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15496
-gerrit
commit 961fae144018d4819d0b4e53e58b640d5d6cb729
Author: sselvar2 <susendra.selvaraj at intel.com>
Date: Thu Jun 9 21:06:34 2016 +0530
intel/amenia: Write protect GPIO relative to bank offset
Update the write protect GPIO reported in ACPI to 35. Also
update the controller ID to "INT3452:01" which will points at
the goldmont device and includes write protect GPIO.
BUG=none
BRANCH=none
TEST=verify crossystem output for wpsw_cur.
Change-Id: Id6b172e289976072836746c1814e0300544a06cb
Signed-off-by: sselvar2 <susendra.selvaraj at intel.com>
Reviewed-on: https://coreboot.intel.com/7771
Reviewed-by: Sparry, Icarus W <icarus.w.sparry at intel.com>
Reviewed-by: Petrov, Andrey <andrey.petrov at intel.com>
Tested-by: Petrov, Andrey <andrey.petrov at intel.com>
---
src/mainboard/intel/amenia/acpi/chromeos.asl | 24 ++++++++++++++++++++++++
src/mainboard/intel/amenia/dsdt.asl | 6 ++++++
2 files changed, 30 insertions(+)
diff --git a/src/mainboard/intel/amenia/acpi/chromeos.asl b/src/mainboard/intel/amenia/acpi/chromeos.asl
new file mode 100644
index 0000000..f6c5ce4
--- /dev/null
+++ b/src/mainboard/intel/amenia/acpi/chromeos.asl
@@ -0,0 +1,24 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/gpio_defs.h>
+
+Name (OIPG, Package () {
+ /* No physical recovery GPIO. */
+ Package () { 0x0001, 0, 0xFFFFFFFF, "INT3452:01" },
+ /* Firmware write protect GPIO. */
+ Package () { 0x0003, 1, 35, "INT3452:01" },
+})
diff --git a/src/mainboard/intel/amenia/dsdt.asl b/src/mainboard/intel/amenia/dsdt.asl
index 4a64f87..4dcb645 100644
--- a/src/mainboard/intel/amenia/dsdt.asl
+++ b/src/mainboard/intel/amenia/dsdt.asl
@@ -37,6 +37,12 @@ DefinitionBlock(
#include <soc/intel/apollolake/acpi/southbridge.asl>
}
}
+
+ #if IS_ENABLED(CONFIG_CHROMEOS)
+ #include "acpi/chromeos.asl"
+ #include <vendorcode/google/chromeos/acpi/chromeos.asl>
+ #endif
+
/* Mainboard Specific devices */
#include "acpi/mainboard.asl"
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