[coreboot-gerrit] Patch set updated for coreboot: mainboard/google/reef: indicate dual rank LPDDR4 skus
Aaron Durbin (adurbin@chromium.org)
gerrit at coreboot.org
Fri Jul 22 06:02:22 CEST 2016
Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15772
-gerrit
commit 692f998d7650e2fffbe6d865126b7bde85bd2539
Author: Aaron Durbin <adurbin at chromium.org>
Date: Thu Jul 21 10:00:39 2016 -0500
mainboard/google/reef: indicate dual rank LPDDR4 skus
The 16Gb devices use two ranks per channel within the DRAM module.
However, the density settings are really on a per rank basis so
indicate dual rank with a device density of 8Gb.
BUG=chrome-os-partner:55446
Change-Id: Ib5dba6f9ed248750d68b726996c71def9b75961e
Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
src/mainboard/google/reef/romstage.c | 26 +++++++++++++++++++-------
1 file changed, 19 insertions(+), 7 deletions(-)
diff --git a/src/mainboard/google/reef/romstage.c b/src/mainboard/google/reef/romstage.c
index 8b7c7a3..74ead51 100644
--- a/src/mainboard/google/reef/romstage.c
+++ b/src/mainboard/google/reef/romstage.c
@@ -71,11 +71,17 @@ static const struct lpddr4_swizzle_cfg board_swizzle = {
#define PROTO_SKU 15
static const struct lpddr4_sku skus[] = {
- /* K4F6E304HB-MGCJ - both logical channels */
+ /*
+ * K4F6E304HB-MGCJ - both logical channels While the parts
+ * are listed at 16Gb there are 2 ranks per channel so indicate
+ * the deneisty as 8Gb per rank.
+ */
[0] = {
.speed = LP4_SPEED_2400,
- .ch0_density = LP4_16Gb_DENSITY,
- .ch1_density = LP4_16Gb_DENSITY,
+ .ch0_density = LP4_8Gb_DENSITY,
+ .ch1_density = LP4_8Gb_DENSITY,
+ .ch0_dual_rank = 1,
+ .ch1_dual_rank = 1,
},
/* K4F8E304HB-MGCJ - both logical channels */
[1] = {
@@ -83,13 +89,19 @@ static const struct lpddr4_sku skus[] = {
.ch0_density = LP4_8Gb_DENSITY,
.ch1_density = LP4_8Gb_DENSITY,
},
- /* MT53B512M32D2NP-062WT:C - both logical channels */
+ /*
+ * MT53B512M32D2NP-062WT:C - both logical channels. While the parts
+ * are listed at 16Gb there are 2 ranks per channel so indicate
+ * the deneisty as 8Gb per rank.
+ */
[2] = {
.speed = LP4_SPEED_2400,
- .ch0_density = LP4_16Gb_DENSITY,
- .ch1_density = LP4_16Gb_DENSITY,
- /* MT53B256M32D1NP-062 WT:C - both logical channels */
+ .ch0_density = LP4_8Gb_DENSITY,
+ .ch1_density = LP4_8Gb_DENSITY,
+ .ch0_dual_rank = 1,
+ .ch1_dual_rank = 1,
},
+ /* MT53B256M32D1NP-062 WT:C - both logical channels */
[3] = {
.speed = LP4_SPEED_2400,
.ch0_density = LP4_8Gb_DENSITY,
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