[coreboot-gerrit] New patch to review for coreboot: drivers/intel/fsp2_0: Monitor FSP setting of MTRRs
Lee Leahy (leroy.p.leahy@intel.com)
gerrit at coreboot.org
Mon Jul 25 21:39:29 CEST 2016
Lee Leahy (leroy.p.leahy at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15849
-gerrit
commit a18bb980e5d49c15e08bd343bea1f249a8cf2943
Author: Lee Leahy <leroy.p.leahy at intel.com>
Date: Sun Jul 24 08:26:06 2016 -0700
drivers/intel/fsp2_0: Monitor FSP setting of MTRRs
Display the MTRR values in the following locations:
* In bootblock - display initial MTTR settings
* Before the call to FspMemoryInit to document coreboot settings
* After the call to FspMemoryInit
* After MTRR setup in postcar to document new coreboot settings
* After the call to FspSiliconInit
* After the call to FspNotify
TEST=Build and run on Galileo Gen2
Change-Id: I8942ef4ca4677501a5c38abaff1c3489eebea53c
Signed-off-by: Lee Leahy <leroy.p.leahy at intel.com>
---
src/arch/x86/exit_car.S | 3 +++
src/drivers/intel/fsp2_0/Makefile.inc | 2 ++
src/drivers/intel/fsp2_0/bootblock.c | 21 +++++++++++++++++++++
src/drivers/intel/fsp2_0/memory_init.c | 8 ++++++++
src/drivers/intel/fsp2_0/notify.c | 4 ++++
src/drivers/intel/fsp2_0/silicon_init.c | 4 ++++
src/soc/intel/common/Makefile.inc | 4 ++++
7 files changed, 46 insertions(+)
diff --git a/src/arch/x86/exit_car.S b/src/arch/x86/exit_car.S
index 69c757d..417070a 100644
--- a/src/arch/x86/exit_car.S
+++ b/src/arch/x86/exit_car.S
@@ -108,6 +108,9 @@ _start:
wrmsr
#endif /* CONFIG_SOC_SETS_MTRRS */
+ /* Display the MTRRs */
+ call soc_display_mtrrs
+
/* Load and run ramstage. */
call copy_and_run
/* Should never return. */
diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc
index ff82390..b7efd23 100644
--- a/src/drivers/intel/fsp2_0/Makefile.inc
+++ b/src/drivers/intel/fsp2_0/Makefile.inc
@@ -13,6 +13,8 @@
ifeq ($(CONFIG_PLATFORM_USES_FSP2_0),y)
+bootblock-y += bootblock.c
+
romstage-y += hand_off_block.c
romstage-y += util.c
romstage-y += memory_init.c
diff --git a/src/drivers/intel/fsp2_0/bootblock.c b/src/drivers/intel/fsp2_0/bootblock.c
new file mode 100644
index 0000000..1d2daed
--- /dev/null
+++ b/src/drivers/intel/fsp2_0/bootblock.c
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#include <bootblock_common.h>
+#include <soc/intel/common/util.h>
+
+__attribute__((weak)) void bootblock_soc_init(void)
+{
+ soc_display_mtrrs();
+}
diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c
index 9276f0c..fdcde7c 100644
--- a/src/drivers/intel/fsp2_0/memory_init.c
+++ b/src/drivers/intel/fsp2_0/memory_init.c
@@ -26,6 +26,7 @@
#include <reset.h>
#include <romstage_handoff.h>
#include <soc/intel/common/mrc_cache.h>
+#include <soc/intel/common/util.h>
#include <string.h>
#include <symbols.h>
#include <timestamp.h>
@@ -237,6 +238,9 @@ static enum fsp_status do_fsp_memory_init(struct fsp_header *hdr, bool s3wake,
if (status != FSP_SUCCESS)
return status;
+ /* Display the MTRRs */
+ soc_display_mtrrs();
+
return do_fsp_post_memory_init(hob_list_ptr, s3wake, hdr->fsp_revision);
}
@@ -298,6 +302,10 @@ enum fsp_status fsp_memory_init(bool s3wake)
struct memranges memmap;
struct range_entry freeranges[2];
+ /* Display the MTRRs */
+ soc_display_mtrrs();
+
+ /* Locate the FSP-M binary */
if (cbfs_boot_locate(&file_desc, name, NULL)) {
printk(BIOS_ERR, "Could not locate %s in CBFS\n", name);
return FSP_NOT_FOUND;
diff --git a/src/drivers/intel/fsp2_0/notify.c b/src/drivers/intel/fsp2_0/notify.c
index bd489d4..1c0a277 100644
--- a/src/drivers/intel/fsp2_0/notify.c
+++ b/src/drivers/intel/fsp2_0/notify.c
@@ -14,6 +14,7 @@
#include <console/console.h>
#include <fsp/api.h>
#include <fsp/util.h>
+#include <soc/intel/common/util.h>
#include <string.h>
#include <timestamp.h>
@@ -56,5 +57,8 @@ enum fsp_status fsp_notify(enum fsp_notify_phase phase)
post_code(POST_FSP_NOTIFY_BEFORE_FINALIZE);
}
+ /* Display the MTRRs */
+ soc_display_mtrrs();
+
return ret;
}
diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c
index 009e151..6f2f229 100644
--- a/src/drivers/intel/fsp2_0/silicon_init.c
+++ b/src/drivers/intel/fsp2_0/silicon_init.c
@@ -19,6 +19,7 @@
#include <fsp/util.h>
#include <lib.h>
#include <program_loading.h>
+#include <soc/intel/common/util.h>
#include <string.h>
#include <timestamp.h>
@@ -63,6 +64,9 @@ static enum fsp_status do_silicon_init(struct fsp_header *hdr)
/* Handle any resets requested by FSPS. */
fsp_handle_reset(status);
+ /* Display the MTRRs */
+ soc_display_mtrrs();
+
return status;
}
diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc
index e9ad508..81ef660 100644
--- a/src/soc/intel/common/Makefile.inc
+++ b/src/soc/intel/common/Makefile.inc
@@ -1,5 +1,7 @@
ifeq ($(CONFIG_SOC_INTEL_COMMON),y)
+bootblock-y += util.c
+
verstage-$(CONFIG_SOC_INTEL_COMMON_LPSS_I2C) += lpss_i2c.c
verstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c
@@ -9,6 +11,8 @@ romstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c
romstage-y += util.c
romstage-$(CONFIG_MMA) += mma.c
+postcar-y += util.c
+
ramstage-y += hda_verb.c
ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c
ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += nvm.c
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