[coreboot-gerrit] Patch merged into coreboot/master: intel sandy/ivy: Redefine DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE
gerrit at coreboot.org
gerrit at coreboot.org
Tue Jul 26 07:09:28 CEST 2016
the following patch was just integrated into master:
commit 9551bed306aa54f5a707bde1d2a934a5341411b8
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date: Wed Jul 20 10:49:38 2016 +0300
intel sandy/ivy: Redefine DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE
Match the definition and use of these variable with haswell, such that
DCACHE_RAM_MRC_VAR_SIZE is not included in DCACHE_RAM_SIZE.
Change-Id: I5af20f63cd0cb631d39f7c7fe0e2a99ebd3ce986
Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
Reviewed-on: https://review.coreboot.org/15761
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter at users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin at chromium.org>
See https://review.coreboot.org/15761 for details.
-gerrit
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