[coreboot-gerrit] Patch set updated for coreboot: skylake/devicetree: Add LPC EC decode range
Subrata Banik (subrata.banik@intel.com)
gerrit at coreboot.org
Tue Jul 26 15:26:43 CEST 2016
Subrata Banik (subrata.banik at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15898
-gerrit
commit 6391710eb750383c98bfbb6c8652224e4789be38
Author: Subrata Banik <subrata.banik at intel.com>
Date: Tue Jul 26 15:37:11 2016 +0530
skylake/devicetree: Add LPC EC decode range
Define LPC decode ranges for EC communication.
BUG=chrome-os-partner:55357
BRANCH=none
TEST=Built and boot kunimitsu to ensure no EC timeout error
Change-Id: Idefdd79e67e89a794195c6821fee16550d1eda53
Signed-off-by: Subrata Banik <subrata.banik at intel.com>
---
src/mainboard/google/chell/devicetree.cb | 3 ++-
src/mainboard/google/glados/devicetree.cb | 3 ++-
src/mainboard/google/lars/devicetree.cb | 3 ++-
src/mainboard/intel/kunimitsu/devicetree.cb | 3 ++-
4 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/src/mainboard/google/chell/devicetree.cb b/src/mainboard/google/chell/devicetree.cb
index 384d374..3f40449 100644
--- a/src/mainboard/google/chell/devicetree.cb
+++ b/src/mainboard/google/chell/devicetree.cb
@@ -13,8 +13,9 @@ chip soc/intel/skylake
register "gpe0_dw1" = "GPP_D"
register "gpe0_dw2" = "GPP_E"
- # EC host command range is in 0x800-0x8ff
+ # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
register "gen1_dec" = "0x00fc0801"
+ register "gen2_dec" = "0x000c0201"
# Enable "Intel Speed Shift Technology"
register "speed_shift_enable" = "1"
diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb
index ff145c5..c315cd9 100644
--- a/src/mainboard/google/glados/devicetree.cb
+++ b/src/mainboard/google/glados/devicetree.cb
@@ -13,8 +13,9 @@ chip soc/intel/skylake
register "gpe0_dw1" = "GPP_D"
register "gpe0_dw2" = "GPP_E"
- # EC host command range is in 0x800-0x8ff
+ # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
register "gen1_dec" = "0x00fc0801"
+ register "gen2_dec" = "0x000c0201"
# Enable "Intel Speed Shift Technology"
register "speed_shift_enable" = "1"
diff --git a/src/mainboard/google/lars/devicetree.cb b/src/mainboard/google/lars/devicetree.cb
index 8ecacdd..e411ad4 100644
--- a/src/mainboard/google/lars/devicetree.cb
+++ b/src/mainboard/google/lars/devicetree.cb
@@ -12,8 +12,9 @@ chip soc/intel/skylake
register "gpe0_dw1" = "GPP_D"
register "gpe0_dw2" = "GPP_E"
- # EC host command range is in 0x800-0x8ff
+ # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
register "gen1_dec" = "0x00fc0801"
+ register "gen2_dec" = "0x000c0201"
# Enable "Intel Speed Shift Technology"
register "speed_shift_enable" = "1"
diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb
index 4aeb0b1..07efd54 100644
--- a/src/mainboard/intel/kunimitsu/devicetree.cb
+++ b/src/mainboard/intel/kunimitsu/devicetree.cb
@@ -12,8 +12,9 @@ chip soc/intel/skylake
register "gpe0_dw1" = "GPP_D"
register "gpe0_dw2" = "GPP_E"
- # EC host command range is in 0x800-0x8ff
+ # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
register "gen1_dec" = "0x00fc0801"
+ register "gen2_dec" = "0x000c0201"
# Enable "Intel Speed Shift Technology"
register "speed_shift_enable" = "1"
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