[coreboot-gerrit] New patch to review for coreboot: intel/fsp_baytrail/i2c: mask i2c interrupts in i2c_init()

[Ben Gardner (gardner.ben@gmail.com)]

Ben Gardner (gardner.ben at gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15047

-gerrit

commit cc49754bba4b7757d833a45a9373fa2012eafc2c
Author: Ben Gardner <gardner.ben at gmail.com>
Date:   Wed Jun 1 09:25:28 2016 -0500

    intel/fsp_baytrail/i2c: mask i2c interrupts in i2c_init()
    
    i2c_init() leaves the I2C device enabled. Combined with the default
    interrupt mask (0x8ff) and the fact that the interrupt line is shared,
    this leads to an interrupt storm in the OS until a proper I2C driver
    is loaded.
    
    This change clears the interrupt mask to prevent the interrupt storm.
    
    Change-Id: I0424a00753d06e26639750f065a7a08a710bfaba
    Signed-off-by: Ben Gardner <gardner.ben at gmail.com>
---
 src/soc/intel/fsp_baytrail/i2c.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/soc/intel/fsp_baytrail/i2c.c b/src/soc/intel/fsp_baytrail/i2c.c
index eb83180..4565ba4 100644
--- a/src/soc/intel/fsp_baytrail/i2c.c
+++ b/src/soc/intel/fsp_baytrail/i2c.c
@@ -141,6 +141,8 @@ int i2c_init(unsigned bus)
 	/* For 400 kHz, the counter value is 0x7d */
 	write32(base_ptr + I2C_FS_SCL_HCNT, 0x7d);
 	write32(base_ptr + I2C_FS_SCL_LCNT, 0x7d);
+	/* no interrupts in BIOS */
+	write32(base_ptr + I2C_INTR_MASK, 0);
 
 	/* Enable the I2C controller for operation */
 	write32(base_ptr + I2C_ENABLE, 0x1);