[coreboot-gerrit] New patch to review for coreboot: intel/apollolake: Clear TSEG reg early in bootblock

[Furquan Shaikh (furquan@google.com)]

Furquan Shaikh (furquan at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15049

-gerrit

commit 16485c5a60e1592aaf8a383ed064ecd83220db69
Author: Furquan Shaikh <furquan at google.com>
Date:   Wed Jun 1 15:09:21 2016 -0700

    intel/apollolake: Clear TSEG reg early in bootblock
    
    TSEG register comes out of reset with a non-zero default value. This
    causes issues when cbmem_top returns non-zero value based on TSEG read
    before DRAM is initialized. Thus, clear TSEG reg early in bootblock to
    avoid unwanted side-effects.
    
    Change-Id: Id3c6c270774108e4caf56e2a07c5072edc65bb58
    Signed-off-by: Furquan Shaikh <furquan at google.com>
---
 src/soc/intel/apollolake/bootblock/bootblock.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c
index b8d6f22..68ce7ab 100644
--- a/src/soc/intel/apollolake/bootblock/bootblock.c
+++ b/src/soc/intel/apollolake/bootblock/bootblock.c
@@ -60,6 +60,12 @@ void asmlinkage bootblock_c_entry(uint32_t tsc_hi, uint32_t tsc_lo)
 
 	/* Set PCI Express BAR */
 	pci_io_write_config32(dev, PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS | 1);
+	/*
+	 * Clear TSEG register - TSEG register comes out of reset with a
+	 * non-zero default value. Clear this register to ensure that there are
+	 * no surprises in CBMEM handling.
+	 */
+	pci_write_config32(dev, TSEG, 0);
 
 	dev = P2SB_DEV;
 	/* BAR and MMIO enable for IOSF, so that GPIOs can be configured */