[coreboot-gerrit] New patch to review for coreboot: google/reef: Add asl code to enable google ChromeEC

[Shaunak Saha (shaunak.saha@intel.com)]

Shaunak Saha (shaunak.saha at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15069

-gerrit

commit 376b7d4b552b440ba10bf2f15731bc27e90bbdde
Author: Shaunak Saha <shaunak.saha at intel.com>
Date:   Fri Jun 3 17:11:12 2016 -0700

    google/reef: Add asl code to enable google ChromeEC
    
    This patch adds asl code to include support for Google ChromeEC.
    We need this to show the battery icon and notifications like charger
    connect/disconnect etc.
    
    BUG = 53096
    TEST = Plug/Unplug AC Adapter multiple times and make sure the battery
           connected is charging properly.
    
    Change-Id: I06f48eda894418514c8ed0136500fff0efd12a35
    Signed-off-by: Shaunak Saha <shaunak.saha at intel.com>
---
 src/mainboard/google/reef/acpi/ec.asl        | 26 ++++++++++++++++++++++++++
 src/mainboard/google/reef/acpi/mainboard.asl | 26 ++++++++++++++++++++++++++
 src/mainboard/google/reef/dsdt.asl           |  3 +++
 src/mainboard/google/reef/ec.h               |  4 ++++
 4 files changed, 59 insertions(+)

diff --git a/src/mainboard/google/reef/acpi/ec.asl b/src/mainboard/google/reef/acpi/ec.asl
new file mode 100644
index 0000000..fe53cb5
--- /dev/null
+++ b/src/mainboard/google/reef/acpi/ec.asl
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/* mainboard configuration */
+#include "../ec.h"
+
+/* Enable EC backed ALS device in ACPI */
+#define EC_ENABLE_ALS_DEVICE
+
+/* Enable EC backed PD MCU device in ACPI */
+#define EC_ENABLE_PD_MCU_DEVICE
+
+/* ACPI code for EC functions */
+#include <ec/google/chromeec/acpi/ec.asl>
diff --git a/src/mainboard/google/reef/acpi/mainboard.asl b/src/mainboard/google/reef/acpi/mainboard.asl
index 05ea06a..06b2efc 100644
--- a/src/mainboard/google/reef/acpi/mainboard.asl
+++ b/src/mainboard/google/reef/acpi/mainboard.asl
@@ -14,3 +14,29 @@
  */
 
 #include "acpi/superio.asl"
+
+Scope (\_SB)
+{
+	Device (LID0)
+	{
+		Name (_HID, EisaId ("PNP0C0D"))
+		Method (_LID, 0)
+		{
+			Return (\_SB.PCI0.LPCB.EC0.LIDS)
+		}
+	}
+
+	Device (PWRB)
+	{
+		Name (_HID, EisaId ("PNP0C0C"))
+	}
+}
+
+/*
+ * LPC Trusted Platform Module
+ */
+Scope (\_SB.PCI0.LPCB)
+{
+	#include <drivers/pc80/tpm/acpi/tpm.asl>
+	#include "ec.asl"
+}
diff --git a/src/mainboard/google/reef/dsdt.asl b/src/mainboard/google/reef/dsdt.asl
index 41bb523..8aa4259 100644
--- a/src/mainboard/google/reef/dsdt.asl
+++ b/src/mainboard/google/reef/dsdt.asl
@@ -25,6 +25,9 @@ DefinitionBlock(
 	/* global NVS and variables */
 	#include <soc/intel/skylake/acpi/globalnvs.asl>
 
+	/* CPU */
+	#include <soc/intel/apollolake/acpi/cpu.asl>
+
 	Scope (\_SB) {
 		Device (PCI0)
 		{
diff --git a/src/mainboard/google/reef/ec.h b/src/mainboard/google/reef/ec.h
index 51d4028..5a32697 100644
--- a/src/mainboard/google/reef/ec.h
+++ b/src/mainboard/google/reef/ec.h
@@ -18,6 +18,10 @@
 
 #include <ec/google/chromeec/ec_commands.h>
 
+/* This is the GPE status bit.
+   TODO: Fix this to proper bit matching GPE routing table */
+#define EC_SCI_GPI   15
+
 #define MAINBOARD_EC_SCI_EVENTS \
 	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)        |\
 	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN)          |\