[coreboot-gerrit] Patch set updated for coreboot: soc/intel/apollolake: Add EMMC DLL API

[Lijian Zhao (lijian.zhao@intel.com)]

Lijian Zhao (lijian.zhao at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15084

-gerrit

commit 34d24ad1b60788a44b20431ca3147ec09f4ef139
Author: Zhao, Lijian <lijian.zhao at intel.com>
Date:   Tue May 17 19:01:34 2016 -0700

    soc/intel/apollolake: Add EMMC DLL API
    
    Newer FSP support to update all the SDIO DLL programming value through
    silicon init upd. Implement the interface to pass board specific
    programming value to fsp silicon init.
    
    Change-Id: Ifd901148f3f7f89f966217491c661ec346337c38
    Signed-off-by: Zhao, Lijian <lijian.zhao at intel.com>
    Reviewed-on: https://chromium.devtools.intel.com/7372
    Reviewed-by: Petrov, Andrey <andrey.petrov at intel.com>
    Tested-by: Petrov, Andrey <andrey.petrov at intel.com>
    Reviewed-on: https://chromium.devtools.intel.com/7585
---
 src/soc/intel/apollolake/chip.c | 4 ++++
 src/soc/intel/apollolake/chip.h | 7 +++++++
 2 files changed, 11 insertions(+)

diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index d9fd794..a37ed22 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -123,6 +123,10 @@ void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *silupd)
 	silconfig->PcieRpClkReqNumber[4] = cfg->pcie_rp4_clkreq_pin;
 	silconfig->PcieRpClkReqNumber[5] = cfg->pcie_rp5_clkreq_pin;
 
+	if (cfg->emmc_tx_data_cntl1 != 0) {
+		silconfig->EmmcTxDataCntl1 = cfg->emmc_tx_data_cntl1;
+	}
+
 	/* Our defaults may not match FSP defaults, so set them explicitly */
 	silconfig->AcpiBase = ACPI_PMIO_BASE;
 	/* First 4k in BAR0 is used for IPC, real registers start at 4k offset */
diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h
index 3d9f5bd..a84eba1 100644
--- a/src/soc/intel/apollolake/chip.h
+++ b/src/soc/intel/apollolake/chip.h
@@ -40,6 +40,13 @@ struct soc_intel_apollolake_config {
 	uint8_t pcie_rp4_clkreq_pin;
 	uint8_t pcie_rp5_clkreq_pin;
 
+	uint32_t emmc_tx_cmd_cntl;
+	uint32_t emmc_tx_data_cntl1;
+	uint32_t emmc_tx_data_cntl2;
+	uint32_t emmc_rx_cmd_data_cntl1;
+	uint32_t emmc_rx_strobe_cntl;
+	uint32_t emmc_rx_cmd_data_cntl2;
+
 	/* Configure serial IRQ (SERIRQ) line. */
 	enum serirq_mode serirq_mode;