[coreboot-gerrit] New patch to review for coreboot: [donotupstream]soc/intel/apollolake: Force HS200

[Lijian Zhao (lijian.zhao@intel.com)]

Lijian Zhao (lijian.zhao at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15091

-gerrit

commit ae0960613df2cb6ce4877d4074c4ea0e8c30e57c
Author: Zhao, Lijian <lijian.zhao at intel.com>
Date:   Mon May 2 14:41:13 2016 -0700

    [donotupstream]soc/intel/apollolake: Force HS200
    
    Force max speed of EMMC to HS200 speed due to some of the amenia board
    in the field can't be trained to running at HS400, limit that to HS200
    can enable lot of board to be operational.
    
    Change-Id: I67d2d52f161af6fbe8cabc97595e5e129627df9e
    Signed-off-by: Zhao, Lijian <lijian.zhao at intel.com>
    Reviewed-on: https://chromium.devtools.intel.com/7367
    Reviewed-by: Petrov, Andrey <andrey.petrov at intel.com>
    Tested-by: Petrov, Andrey <andrey.petrov at intel.com>
    Reviewed-on: https://chromium.devtools.intel.com/7583
---
 src/soc/intel/apollolake/chip.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index 84628a3..d9fd794 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -128,8 +128,9 @@ void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *silupd)
 	/* First 4k in BAR0 is used for IPC, real registers start at 4k offset */
 	silconfig->PmcBase = PMC_BAR0 + 0x1000;
 	silconfig->P2sbBase = P2SB_BAR;
-
 	silconfig->IshEnable = cfg->integrated_sensor_hub_enable;
+	/* Force to run HS200 temporary for some platform failed to running at HS400 */
+	silconfig->eMMCHostMaxSpeed = 1;
 }
 
 struct chip_operations soc_intel_apollolake_ops = {