[coreboot-gerrit] Patch set updated for coreboot: apollolake/amenia: Adding NHLA and NHLL, address and length of NHLT table in ACPI. Also including globalnvs in Amenia.

[Lijian Zhao (lijian.zhao@intel.com)]

Lijian Zhao (lijian.zhao at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15025

-gerrit

commit 2f19fd91a2a3ee170d527b7c6570cd6ad97441d1
Author: Saurabh Satija <saurabh.satija at intel.com>
Date:   Thu Mar 31 15:41:30 2016 -0700

    apollolake/amenia: Adding NHLA and NHLL, address and length of NHLT table
    	in ACPI. Also including globalnvs in Amenia.
    
    Change-Id: Ic0959a8aae18d54e10e3fcd95bfc98a6b6e0385a
    Signed-off-by: Saurabh Satija <saurabh.satija at intel.com>
    Reviewed-on: https://chromium.devtools.intel.com/7142
    Reviewed-by: Petrov, Andrey <andrey.petrov at intel.com>
    Reviewed-on: https://chromium.devtools.intel.com/7574
    Tested-by: Petrov, Andrey <andrey.petrov at intel.com>
---
 src/mainboard/intel/amenia/dsdt.asl         | 3 +++
 src/soc/intel/apollolake/acpi/globalnvs.asl | 7 ++-----
 src/soc/intel/apollolake/include/soc/nvs.h  | 9 +++------
 3 files changed, 8 insertions(+), 11 deletions(-)

diff --git a/src/mainboard/intel/amenia/dsdt.asl b/src/mainboard/intel/amenia/dsdt.asl
index 19e7360..8147c27 100644
--- a/src/mainboard/intel/amenia/dsdt.asl
+++ b/src/mainboard/intel/amenia/dsdt.asl
@@ -24,6 +24,9 @@ DefinitionBlock(
 	0x20110725	// OEM revision
 )
 {
+	// global NVS and variables
+	#include <soc/intel/apollolake/acpi/globalnvs.asl>
+
 	Scope (\_SB) {
 		Device (PCI0)
 		{
diff --git a/src/soc/intel/apollolake/acpi/globalnvs.asl b/src/soc/intel/apollolake/acpi/globalnvs.asl
index e081dcb..3efca51 100644
--- a/src/soc/intel/apollolake/acpi/globalnvs.asl
+++ b/src/soc/intel/apollolake/acpi/globalnvs.asl
@@ -28,11 +28,8 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
 {
 	/* Miscellaneous */
 	Offset (0x00),
-	PCNT,	8,      // 0x01 - Processor Count
-	PPCM,	8,      // 0x02 - Max PPC State
-	LIDS,	8,      // 0x03 - LID State
-	PWRS,	8,      // 0x04 - AC Power State
-	DPTE,	8,      // 0x05 - Enable DPTF
+	NHLA,	64,	// 0x00 - NHLT Address
+	NHLL,	32,	// 0x08 - NHLT Length
 
 	/* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */
 	Offset (0x100),
diff --git a/src/soc/intel/apollolake/include/soc/nvs.h b/src/soc/intel/apollolake/include/soc/nvs.h
index 4768aaa..23e40e8 100644
--- a/src/soc/intel/apollolake/include/soc/nvs.h
+++ b/src/soc/intel/apollolake/include/soc/nvs.h
@@ -28,12 +28,9 @@
 
 struct global_nvs_t {
 	/* Miscellaneous */
-	uint8_t	pcnt; /* 0x01 - Processor Count */
-	uint8_t	ppcm; /* 0x02 - Max PPC State */
-	uint8_t	lids; /* 0x03 - LID State */
-	uint8_t	pwrs; /* 0x04 - AC Power State */
-	uint8_t	dpte; /* 0x05 - Enable DPTF */
-	uint8_t	unused[251];
+	u64     nhla; /* 0x00 - NHLT Address */
+	u32     nhll; /* 0x08 - NHLT Length */
+	uint8_t unused[244];
 
 	/* ChromeOS specific (0x100 - 0xfff) */
 	chromeos_acpi_t chromeos;