[coreboot-gerrit] Patch set updated for coreboot: Amenia: Program EMMC dll setting

[Lijian Zhao (lijian.zhao@intel.com)]

Lijian Zhao (lijian.zhao at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15092

-gerrit

commit 51c70a8e98d90bfd4cabfea9bdd513541fea9eaa
Author: Zhao, Lijian <lijian.zhao at intel.com>
Date:   Tue May 17 19:26:18 2016 -0700

    Amenia: Program EMMC dll setting
    
    EMMC TX DATA Control need to be programmed to 0x1A1A, otherwise EMMC
    can not be running stable on HS400 speed.
    
    Change-Id: I42c23ff7e6956e75de5e1b1339a570b35d999301
    Signed-off-by: Zhao, Lijian <lijian.zhao at intel.com>
    Reviewed-on: https://chromium.devtools.intel.com/7373
    Reviewed-by: Petrov, Andrey <andrey.petrov at intel.com>
    Tested-by: Petrov, Andrey <andrey.petrov at intel.com>
    Reviewed-on: https://chromium.devtools.intel.com/7586
---
 src/mainboard/intel/amenia/devicetree.cb | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/intel/amenia/devicetree.cb b/src/mainboard/intel/amenia/devicetree.cb
index af06848..6b934c4 100644
--- a/src/mainboard/intel/amenia/devicetree.cb
+++ b/src/mainboard/intel/amenia/devicetree.cb
@@ -9,6 +9,7 @@ chip soc/intel/apollolake
 
 	# Integrated Sensor Hub
 	register "integrated_sensor_hub_enable" = "0"
+	register "emmc_tx_data_cntl1" = "0x1A1A" # HS400 required
 
 	device domain 0 on
 		device pci 00.0 on end	# - Host Bridge