[coreboot-gerrit] Patch set updated for coreboot: gru: kevin: enable EC SPI interface

[Martin Roth (martinroth@google.com)]

Martin Roth (martinroth at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15032

-gerrit

commit aa2972676ca8fa7c2bb20e2a570978efd66e7897
Author: Vadim Bendebury <vbendeb at chromium.org>
Date:   Sun May 22 16:25:29 2016 -0700

    gru: kevin: enable EC SPI interface
    
    This configures and enables SPI interface #5 used for EC
    communications on Gru/Kevin.
    
    BRANCH=none
    BUG=chrome-os-partner:51537
    TEST=with the appropriate depthcharge change it is possible to trigger
         booting Chrome OS from the SD card by pressing '^U' on Gru
         keyboard at the right time.
    
    Change-Id: I5304bf47e030c0b9b7794752f30ffdca6c03a4f4
    Signed-off-by: Martin Roth <martinroth at chromium.org>
    Original-Commit-Id: b5cc177
    Original-Change-Id: I99883daa60562ccddfaeb858c1957d497f05a501
    Original-Signed-off-by: Vadim Bendebury <vbendeb at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/346632
---
 src/mainboard/google/gru/Kconfig     | 2 +-
 src/mainboard/google/gru/bootblock.c | 7 +++++--
 2 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/src/mainboard/google/gru/Kconfig b/src/mainboard/google/gru/Kconfig
index 48ae698..39cbf08 100644
--- a/src/mainboard/google/gru/Kconfig
+++ b/src/mainboard/google/gru/Kconfig
@@ -56,7 +56,7 @@ config DRAM_SIZE_MB
 
 config EC_GOOGLE_CHROMEEC_SPI_BUS
 	hex
-	default 0
+	default 5
 
 config BOOT_MEDIA_SPI_BUS
 	int
diff --git a/src/mainboard/google/gru/bootblock.c b/src/mainboard/google/gru/bootblock.c
index a048188..19e2cde 100644
--- a/src/mainboard/google/gru/bootblock.c
+++ b/src/mainboard/google/gru/bootblock.c
@@ -59,11 +59,14 @@ void bootblock_mainboard_early_init(void)
 
 void bootblock_mainboard_init(void)
 {
-	/* select the pinmux for spi flashrom */
+	/* Set pinmux and configure spi flashrom. */
 	write32(&rk3399_pmugrf->spi1_rxd, IOMUX_SPI1_RX);
 	write32(&rk3399_pmugrf->spi1_csclktx, IOMUX_SPI1_CSCLKTX);
-
 	rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 24750*KHz);
 
+	/* Set pinmux and configure EC flashrom. */
+	write32(&rk3399_grf->iomux_spi5, IOMUX_SPI5);
+	rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, 3093750);
+
 	setup_chromeos_gpios();
 }