[coreboot-gerrit] New patch to review for coreboot: soc/apollolake: Set max snoop and non-snoop latency

[Hannah Williams (hannah.williams@intel.com)]

Hannah Williams (hannah.williams at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15123

-gerrit

commit eb1d3818dc68d358fc35468ee7016f07aa885000
Author: Hannah Williams <hannah.williams at intel.com>
Date:   Mon May 2 10:08:09 2016 -0700

    soc/apollolake: Set max snoop and non-snoop latency
    
    Change-Id: I712010d49ca5765503d9534d12b09facbfed0a3e
    Signed-off-by: Hannah Williams <hannah.williams at intel.com>
    Signed-off-by: Hannah Williams <hannah.williams at intel.com>
---
 src/soc/intel/apollolake/Makefile.inc          |  1 +
 src/soc/intel/apollolake/include/soc/pci_ids.h |  6 ++
 src/soc/intel/apollolake/pcie.c                | 91 ++++++++++++++++++++++++++
 3 files changed, 98 insertions(+)

diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc
index 9e4e160..96be53f 100644
--- a/src/soc/intel/apollolake/Makefile.inc
+++ b/src/soc/intel/apollolake/Makefile.inc
@@ -49,6 +49,7 @@ ramstage-y += uart.c
 ramstage-y += northbridge.c
 ramstage-y += spi.c
 ramstage-y += tsc_freq.c
+ramstage-y += pcie.c
 ramstage-y += pmutil.c
 ramstage-y += pmc.c
 ramstage-y += smi.c
diff --git a/src/soc/intel/apollolake/include/soc/pci_ids.h b/src/soc/intel/apollolake/include/soc/pci_ids.h
index 0790c6e..c8f641b 100644
--- a/src/soc/intel/apollolake/include/soc/pci_ids.h
+++ b/src/soc/intel/apollolake/include/soc/pci_ids.h
@@ -25,6 +25,12 @@
 #define PCI_DEVICE_ID_APOLLOLAKE_HWSEQ_SPI	0x5a96		/* 00:0d.2 */
 #define PCI_DEVICE_ID_APOLLOLAKE_AUDIO		0x5a98		/* 00:0e.0 */
 #define PCI_DEVICE_ID_APOLLOLAKE_SATA		0x5ae0		/* 00:12.0 */
+#define PCI_DEVICE_ID_APOLLOLAKE_PCIE_A0	0x5ad8		/* 00:13.0 */
+#define PCI_DEVICE_ID_APOLLOLAKE_PCIE_A1	0x5ad9		/* 00:13.1 */
+#define PCI_DEVICE_ID_APOLLOLAKE_PCIE_A2	0x5ada		/* 00:13.2 */
+#define PCI_DEVICE_ID_APOLLOLAKE_PCIE_A3	0x5adb		/* 00:13.3 */
+#define PCI_DEVICE_ID_APOLLOLAKE_PCIE_B0	0x5ad6		/* 00:14.0 */
+#define PCI_DEVICE_ID_APOLLOLAKE_PCIE_B1	0x5ad7		/* 00:14.1 */
 #define PCI_DEVICE_ID_APOLLOLAKE_I2C0		0x5aac		/* 00:16.0 */
 #define PCI_DEVICE_ID_APOLLOLAKE_I2C1		0x5aae		/* 00:16.1 */
 #define PCI_DEVICE_ID_APOLLOLAKE_I2C2		0x5ab0		/* 00:16.2 */
diff --git a/src/soc/intel/apollolake/pcie.c b/src/soc/intel/apollolake/pcie.c
new file mode 100644
index 0000000..472f42f
--- /dev/null
+++ b/src/soc/intel/apollolake/pcie.c
@@ -0,0 +1,91 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015-2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pciexp.h>
+#include <device/pci_def.h>
+#include <device/pci_ids.h>
+#include <soc/pci_devs.h>
+#include <soc/pci_ids.h>
+#include <delay.h>
+
+static void pch_pcie_init(struct device *dev)
+{
+	u16 reg16;
+	u32 reg32;
+
+	/* Enable SERR */
+	reg32 = pci_read_config32(dev, PCI_COMMAND);
+	reg32 |= PCI_COMMAND_SERR;
+	pci_write_config32(dev, PCI_COMMAND, reg32);
+
+	/* Enable Bus Master */
+	reg32 = pci_read_config32(dev, PCI_COMMAND);
+	reg32 |= PCI_COMMAND_MASTER;
+	pci_write_config32(dev, PCI_COMMAND, reg32);
+
+	/* Set Cache Line Size to 0x10 */
+	pci_write_config8(dev, 0x0c, 0x10);
+
+	reg16 = pci_read_config16(dev, 0x3e);
+	reg16 &= ~(1 << 0); /* disable parity error response */
+	reg16 |= (1 << 2); /* ISA enable */
+	pci_write_config16(dev, 0x3e, reg16);
+
+	/* Clear errors in status registers */
+	reg16 = pci_read_config16(dev, 0x06);
+	pci_write_config16(dev, 0x06, reg16);
+	reg16 = pci_read_config16(dev, 0x1e);
+	pci_write_config16(dev, 0x1e, reg16);
+}
+
+static void pcie_set_L1_ss_max_latency(device_t dev, unsigned int off)
+{
+	/* Set max snoop and non-snoop latency for the SOC */
+	pci_mmio_write_config32(dev, off, 0x10031003);
+}
+
+static struct pci_operations pcie_ops = {
+	.set_L1_ss_latency = pcie_set_L1_ss_max_latency,
+};
+
+static struct device_operations device_ops = {
+	.read_resources		= pci_bus_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pci_bus_enable_resources,
+	.init			= pch_pcie_init,
+	.enable			= NULL,
+	.scan_bus		= pciexp_scan_bridge,
+	.ops_pci		= &pcie_ops,
+};
+
+static const unsigned short pcie_device_ids[] = {
+	PCI_DEVICE_ID_APOLLOLAKE_PCIE_A0,
+	PCI_DEVICE_ID_APOLLOLAKE_PCIE_A1,
+	PCI_DEVICE_ID_APOLLOLAKE_PCIE_A2,
+	PCI_DEVICE_ID_APOLLOLAKE_PCIE_A3,
+	PCI_DEVICE_ID_APOLLOLAKE_PCIE_B0,
+	PCI_DEVICE_ID_APOLLOLAKE_PCIE_B1,
+};
+
+static const struct pci_driver pch_pcie __pci_driver = {
+	.ops	 = &device_ops,
+	.vendor	 = PCI_VENDOR_ID_INTEL,
+	.devices = pcie_device_ids,
+};