[coreboot-gerrit] New patch to review for coreboot: soc/intel/apollolake: Include _PTS, _WAK and _SWS

[Hannah Williams (hannah.williams@intel.com)]

Hannah Williams (hannah.williams at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15138

-gerrit

commit 9bba50151a7ecb73c7b33fc9d9952a5fde2f6048
Author: Hannah Williams <hannah.williams at intel.com>
Date:   Wed Jun 8 17:39:37 2016 -0700

    soc/intel/apollolake: Include _PTS, _WAK and _SWS
    
    Change-Id: I3400611095978421c7b35a7ea9c68b8571942ae9
    Signed-off-by: Hannah Williams <hannah.williams at intel.com>
---
 src/soc/intel/apollolake/acpi/globalnvs.asl |  2 ++
 src/soc/intel/apollolake/acpi/platform.asl  | 20 ++++++++++++++++++++
 src/soc/intel/apollolake/include/soc/nvs.h  |  4 +++-
 3 files changed, 25 insertions(+), 1 deletion(-)

diff --git a/src/soc/intel/apollolake/acpi/globalnvs.asl b/src/soc/intel/apollolake/acpi/globalnvs.asl
index e081dcb..1ec95b0 100644
--- a/src/soc/intel/apollolake/acpi/globalnvs.asl
+++ b/src/soc/intel/apollolake/acpi/globalnvs.asl
@@ -33,6 +33,8 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
 	LIDS,	8,      // 0x03 - LID State
 	PWRS,	8,      // 0x04 - AC Power State
 	DPTE,	8,      // 0x05 - Enable DPTF
+	PM1I,   64,     // 0x06 - System Wake Source - PM1 Index
+	GPEI,   64,     // 0x0E - GPE Wake Source
 
 	/* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */
 	Offset (0x100),
diff --git a/src/soc/intel/apollolake/acpi/platform.asl b/src/soc/intel/apollolake/acpi/platform.asl
new file mode 100644
index 0000000..f3202a0
--- /dev/null
+++ b/src/soc/intel/apollolake/acpi/platform.asl
@@ -0,0 +1,20 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2012 Google Inc.
+ * Copyright (C) 2016 Intel Corp
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/* Enable ACPI _SWS methods */
+#include <soc/intel/common/acpi/acpi_wake_source.asl>
+#include <soc/intel/common/acpi/platform.asl>
diff --git a/src/soc/intel/apollolake/include/soc/nvs.h b/src/soc/intel/apollolake/include/soc/nvs.h
index 4768aaa..380ef34 100644
--- a/src/soc/intel/apollolake/include/soc/nvs.h
+++ b/src/soc/intel/apollolake/include/soc/nvs.h
@@ -33,7 +33,9 @@ struct global_nvs_t {
 	uint8_t	lids; /* 0x03 - LID State */
 	uint8_t	pwrs; /* 0x04 - AC Power State */
 	uint8_t	dpte; /* 0x05 - Enable DPTF */
-	uint8_t	unused[251];
+	u64     pm1i; /* 0x06 - System Wake Source - PM1 Index */
+	u64     gpei; /* 0x0E - GPE Wake Source */
+	uint8_t	unused[239];
 
 	/* ChromeOS specific (0x100 - 0xfff) */
 	chromeos_acpi_t chromeos;