[coreboot-gerrit] Patch merged into coreboot/master: soc/intel/common: Add LPSS I2C driver

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 8a14c39ac6c4ef3ed960d79aaf9e7c56b595f8f2
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Tue Jun 7 13:40:11 2016 -0700

    soc/intel/common: Add LPSS I2C driver
    
    Add a generic LPSS I2C driver for Intel SOCs that use the Synopsys
    DesignWare I2C block and have a similar configuration of that block.
    
    This driver is ported from the Chromium depthcharge project where it
    was ported from U-Boot originally, though it looks very different now.
    From depthcharge it has been modified to fit into the coreboot I2C
    driver model with platform_i2c_transfer() and use coreboot semantics
    throughout including the stopwatch API for timeouts.
    
    In order for this shared driver to work the SOC must:
    
    1) Define CONFIG_SOC_INTEL_COMMON_LPSS_I2C_CLOCK_MHZ to set the clock
    speed that the I2C controller core is running at.
    
    2) Define the lpss_i2c_base_address() function to return the base
    address for the specified bus.  This could be either done by looking
    up the PCI device or a static table if the controllers are not PCI
    devices and just have a static base address.
    
    The driver is usable in verstage/romstage/ramstage, though it does
    require early initialization of the controller to set a temporary base
    address if it is used outside of ramstage.
    
    This has been tested on Broadwell and Skylake SOCs in both pre-RAM and
    ramstage environments by reading and writing both single bytes across
    multiple segments as well as large blocks of data at once and with
    different configured bus speeds.
    
    While it does need specific configuration for each SOC this driver
    should be able to work on all Intel SOCs currently in src/soc/intel.
    
    Change-Id: Ibe492e53c45edb1d1745ec75e1ff66004081717e
    Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Reviewed-on: https://review.coreboot.org/15101
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See https://review.coreboot.org/15101 for details.

-gerrit