[coreboot-gerrit] Patch merged into coreboot/master: skylake: gpio: Add support for setting 1.8V tolerant

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 7f3156dad67ad35f02afedd85cdf4a19e3c0875e
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Mon Jun 6 17:13:42 2016 -0700

    skylake: gpio: Add support for setting 1.8V tolerant
    
    Add the voltage tolerance GPIO attribute for configuring I2C/I2S buses
    that are at 1.8V.  This is currently done by passing in a value to FSP
    but it is needed earlier than FSP if the I2C bus is used in verstage.
    
    This does not remove the need for the FSP input parameter, that is
    still required so FSP doesn't disable what has been set in coreboot.
    The mainboards that are affected are updated in this commit.
    
    This was tested by exercising I2C transactions to the 1.8V codec while
    in verstage on the google/chell mainboard.
    
    Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Change-Id: I93d22c2e3bc0617c87f03c37a8746e22a112cc9c
    Reviewed-on: https://review.coreboot.org/15103
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Tested-by: build bot (Jenkins)


See https://review.coreboot.org/15103 for details.

-gerrit