[coreboot-gerrit] Patch merged into coreboot/master: skylake: Support common LPSS I2C driver

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 4001f244ad765d6110570fe7217fc05e7dfb949e
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Tue Jun 7 16:40:19 2016 -0700

    skylake: Support common LPSS I2C driver
    
    Support the common Intel LPSS I2C driver for the 6 I2C bus controllers
    that are present on the Skylake-LP PCH with a 120 mHz clock.  The
    required lpss_i2c_base_address() method is implemented separately for
    verstage/romstage and ramstage environments.
    
    This provides methods to convert to and from "struct device" and the
    I2C controller bus number for that device.  These are used to provide
    support for the "I2C Bus Operations" that are present in the coreboot
    devicetree.
    
    To support the I2C controller before ramstage an early init function
    is provided to do minimal initializaiton of the PCI device and assign
    a temporary base address for use before memory.  The final base
    address is assigned during device enumeration and used during ramstage.
    
    Because it is usually not necessary to enable I2C controllers before
    ramstage a config register for the devicetree is provided to perform
    early initialization of this controller.  In addition the bus speed
    can be set in the devicetree and that speed will be applied when the
    device is initialized.  If not provided the default speed is set to
    I2C_SPEED_FAST.
    
    This was tested with the google/chell mainboard by reading and writing
    from the trackpad and codec devices during both verstage and ramstage.
    
    Change-Id: Ia0270adfaf2843a3be4e00c732c85401a3401ef5
    Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Reviewed-on: https://review.coreboot.org/15105
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Tested-by: build bot (Jenkins)


See https://review.coreboot.org/15105 for details.

-gerrit