[coreboot-gerrit] Patch set updated for coreboot: intel/apollolake: Use custom reset calls

[Furquan Shaikh (furquan@google.com)]

Furquan Shaikh (furquan at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15143

-gerrit

commit 85c92c3a8278883529f6ed557f36704895afcada
Author: Furquan Shaikh <furquan at google.com>
Date:   Thu Jun 9 21:35:50 2016 -0700

    intel/apollolake: Use custom reset calls
    
    Due to USB LDO issue in current steppings, cold reboot needs to be
    temporarily disabled. Thus, hard_reset call should be the same as
    soft_reset.
    
    Once future steppings are available INTEL_COMMON_RESET can be enabled again.
    
    Change-Id: If0ec56db3864d500acc93d2b363a78a6cd7632da
    Signed-off-by: Furquan Shaikh <furquan at google.com>
---
 src/soc/intel/apollolake/Kconfig      |  4 ++-
 src/soc/intel/apollolake/Makefile.inc |  3 ++
 src/soc/intel/apollolake/reset.c      | 54 +++++++++++++++++++++++++++++++++++
 3 files changed, 60 insertions(+), 1 deletion(-)

diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index 98ce7d8..d830a9f 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -59,9 +59,11 @@ config TPM_ON_FAST_SPI
 	 TPM part is conntected on Fast SPI interface, but the LPC MMIO
 	 TPM transactions are decoded and serialized over the SPI interface.
 
+# TODO(furquan): Use common reset once USB LDO issue is resolved in future
+# steppings.
 config SOC_INTEL_COMMON_RESET
 	bool
-	default y
+	default n
 
 config MMCONF_BASE_ADDRESS
 	hex "PCI MMIO Base Address"
diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc
index 9e4e160..a03ac49 100644
--- a/src/soc/intel/apollolake/Makefile.inc
+++ b/src/soc/intel/apollolake/Makefile.inc
@@ -28,6 +28,7 @@ romstage-y += meminit.c
 romstage-y += mmap_boot.c
 romstage-y += tsc_freq.c
 romstage-y += pmutil.c
+romstage-y += reset.c
 
 smm-y += mmap_boot.c
 smm-y += pmutil.c
@@ -52,6 +53,7 @@ ramstage-y += tsc_freq.c
 ramstage-y += pmutil.c
 ramstage-y += pmc.c
 ramstage-y += smi.c
+ramstage-y += reset.c
 
 postcar-y += exit_car.S
 postcar-y += memmap.c
@@ -65,6 +67,7 @@ verstage-y += mmap_boot.c
 verstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
 verstage-y += tsc_freq.c
 verstage-y += pmutil.c
+verstage-y += reset.c
 
 CPPFLAGS_common += -I$(src)/soc/intel/apollolake/include
 
diff --git a/src/soc/intel/apollolake/reset.c b/src/soc/intel/apollolake/reset.c
new file mode 100644
index 0000000..efae0cd
--- /dev/null
+++ b/src/soc/intel/apollolake/reset.c
@@ -0,0 +1,54 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2014-2016 Google Inc.
+ * Copyright (C) 2015 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/hlt.h>
+#include <arch/io.h>
+#include <reset.h>
+
+/* Reset control port */
+#define RST_CNT			0xcf9
+#define FULL_RST			(1 << 3)
+#define RST_CPU			(1 << 2)
+#define SYS_RST			(1 << 1)
+
+
+/*
+ * Temporary disable cold reboot on Apollolake platform due to USB LDO issue.
+ * Should be fixed in later stepping.
+ */
+void hard_reset(void)
+{
+	outb(RST_CPU | SYS_RST, RST_CNT);
+	while (1)
+		hlt();
+}
+
+void soft_reset(void)
+{
+	/* PMC_PLTRST# asserted. */
+	outb(RST_CPU | SYS_RST, RST_CNT);
+	while (1)
+		hlt();
+}
+
+void cpu_reset(void)
+{
+	/* Sends INIT# to CPU */
+	outb(RST_CPU, RST_CNT);
+	while (1)
+		hlt();
+}