[coreboot-gerrit] Patch set updated for coreboot: google/reef: Device tree updates

Furquan Shaikh (furquan@google.com) gerrit at coreboot.org
Fri Jun 10 14:32:11 CEST 2016


Furquan Shaikh (furquan at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15142

-gerrit

commit 91215ae5cffbb3337ce9427ce86859a0ee840799
Author: Furquan Shaikh <furquan at google.com>
Date:   Thu Jun 9 15:14:14 2016 -0700

    google/reef: Device tree updates
    
    1. Keep ISH enabled for now
    2. Program emmc dll setting
    
    Change-Id: Id9cb276eed8d027ab6d2e81a5ec962bc730c1ff5
    Signed-off-by: Furquan Shaikh <furquan at google.com>
---
 src/mainboard/google/reef/devicetree.cb | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/src/mainboard/google/reef/devicetree.cb b/src/mainboard/google/reef/devicetree.cb
index f442872..a1ed9f3 100644
--- a/src/mainboard/google/reef/devicetree.cb
+++ b/src/mainboard/google/reef/devicetree.cb
@@ -6,6 +6,14 @@ chip soc/intel/apollolake
 
 	register "pcie_rp4_clkreq_pin" = "0"    # wifi/bt
 
+	# Integrated Sensor Hub
+	register "integrated_sensor_hub_enable" = "1"
+
+	# EMMC TX DATA Delay 1#
+	# 0x1A[14:8] stands for 26*125 = 3250 pSec delay for HS400
+	# 0x1A[6:0] stands for 26*125 = 3250 pSec delay for SDR104/HS200
+	register "emmc_tx_data_cntl1" = "0x1A1A" # HS400 required
+
 	device domain 0 on
 		device pci 00.0 on  end	# - Host Bridge
 		device pci 00.1 on  end	# - DPTF



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