[coreboot-gerrit] Patch set updated for coreboot: [WIP] bd82x6x: Enable SATA hot plug (not working yet)
Iru Cai (mytbk920423@gmail.com)
gerrit at coreboot.org
Fri Jun 10 16:14:21 CEST 2016
Iru Cai (mytbk920423 at gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14635
-gerrit
commit d6b035b2d89874fd632c30fb92dc25cce2702e6d
Author: Iru Cai <mytbk920423 at gmail.com>
Date: Sat May 7 00:35:47 2016 +0800
[WIP] bd82x6x: Enable SATA hot plug (not working yet)
This change is going to enable hot plug on SATA ports like DVD drive
and eSATA port.
TODO: The port control registers are changed after SATA controller is
initialized, but I don't know where they change. I'm going to dump
these registers before OS loads.
Change-Id: Id959145b1ebe87fdcadc7a062a1de9b217e58dd4
Signed-off-by: Iru Cai <mytbk920423 at gmail.com>
---
src/mainboard/lenovo/t420/devicetree.cb | 4 ++-
src/mainboard/lenovo/t520/devicetree.cb | 2 ++
src/southbridge/intel/bd82x6x/chip.h | 1 +
src/southbridge/intel/bd82x6x/sata.c | 51 ++++++++++++++++++++++++++++++++-
4 files changed, 56 insertions(+), 2 deletions(-)
diff --git a/src/mainboard/lenovo/t420/devicetree.cb b/src/mainboard/lenovo/t420/devicetree.cb
index 9f42cbb..23c164f 100644
--- a/src/mainboard/lenovo/t420/devicetree.cb
+++ b/src/mainboard/lenovo/t420/devicetree.cb
@@ -55,7 +55,9 @@ chip northbridge/intel/sandybridge
register "gpi13_routing" = "2"
# Enable SATA ports 0 (HDD bay) & 1 (ODD bay) & 2 (mSATA) & 3 (eSATA) & 4 (dock)
+ # support hot plug on ODD bay and eSATA
register "sata_port_map" = "0x1f"
+ register "esata_port_map" = "0x0a"
# Set max SATA speed to 6.0 Gb/s
register "sata_interface_speed_support" = "0x3"
@@ -63,7 +65,7 @@ chip northbridge/intel/sandybridge
register "gen2_dec" = "0x0c15e1"
register "gen4_dec" = "0x0c06a1"
- register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }"
+ register "pcie_hotplug_map" = "{ 1, 0, 0, 1, 0, 0, 0, 0 }"
# Enable zero-based linear PCIe root port functions
register "pcie_port_coalesce" = "1"
diff --git a/src/mainboard/lenovo/t520/devicetree.cb b/src/mainboard/lenovo/t520/devicetree.cb
index 379a95d..f4fc6675e 100644
--- a/src/mainboard/lenovo/t520/devicetree.cb
+++ b/src/mainboard/lenovo/t520/devicetree.cb
@@ -51,7 +51,9 @@ chip northbridge/intel/sandybridge
register "gpi13_routing" = "2"
# Enable SATA ports 0 (HDD bay) & 1 (ODD bay) & 2 (mSATA) & 3 (eSATA) & 4 (dock)
+ # support hot plug on ODD bay and eSATA
register "sata_port_map" = "0x1f"
+ register "esata_port_map" = "0x0a"
# Set max SATA speed to 6.0 Gb/s
register "sata_interface_speed_support" = "0x3"
diff --git a/src/southbridge/intel/bd82x6x/chip.h b/src/southbridge/intel/bd82x6x/chip.h
index e1064a7..6b2dcf3 100644
--- a/src/southbridge/intel/bd82x6x/chip.h
+++ b/src/southbridge/intel/bd82x6x/chip.h
@@ -48,6 +48,7 @@ struct southbridge_intel_bd82x6x_config {
/* IDE configuration */
uint8_t sata_port_map;
+ uint8_t esata_port_map;
uint32_t sata_port0_gen3_tx;
uint32_t sata_port1_gen3_tx;
diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c
index d217a04..fecedd1 100644
--- a/src/southbridge/intel/bd82x6x/sata.c
+++ b/src/southbridge/intel/bd82x6x/sata.c
@@ -102,7 +102,14 @@ static void sata_init(struct device *dev)
/* CAP (HBA Capabilities) : enable power management */
reg32 = read32(abar + 0x00);
reg32 |= 0x0c006000; // set PSC+SSC+SALP+SSS
- reg32 &= ~0x00020060; // clear SXS+EMS+PMS
+ reg32 &= ~0x00020040; // clear EMS+PMS
+ /* clear SXS, if no eSATA port is available, otherwise set it */
+ if (config->esata_port_map==0) {
+ printk(BIOS_DEBUG, "esata_port_map = %02x\n", config->esata_port_map);
+ reg32 &= ~0x00000020;
+ } else {
+ reg32 |= 0x00000020;
+ }
/* Set ISS, if available */
if (config->sata_interface_speed_support)
{
@@ -111,6 +118,8 @@ static void sata_init(struct device *dev)
<< 20;
}
write32(abar + 0x00, reg32);
+ reg32 = read32(abar + 0x00);
+ printk(BIOS_DEBUG, "CAP register value: 0x%08x.\n", reg32);
/* PI (Ports implemented) */
write32(abar + 0x0c, config->sata_port_map);
(void) read32(abar + 0x0c); /* Read back 1 */
@@ -123,6 +132,46 @@ static void sata_init(struct device *dev)
reg32 = read32(abar + 0xa0);
reg32 &= ~0x00000005;
write32(abar + 0xa0, reg32);
+ /* Enable SATA hot plug */
+ if (config->esata_port_map) {
+ printk(BIOS_DEBUG, "Enable SATA hot plug.\n");
+ u8 *port_control_reg = abar+0x100;
+ for (uint8_t emap=config->esata_port_map;
+ emap;
+ emap>>=1, port_control_reg += 0x80) {
+ if ((emap&1)==0) {
+ printk(BIOS_DEBUG, "not eSATA, skip.\n");
+ continue;
+ }
+ /* set PxIE.PRCE (bit 22) */
+ u8 *PxIE = port_control_reg+0x14;
+ reg32 = read32(PxIE);
+ printk(BIOS_DEBUG, "changing PxIE: 0x%08x.\n", reg32);
+ reg32 |= 0x00400000;
+ write32(PxIE, reg32);
+ reg32 = read32(PxIE);
+ printk(BIOS_DEBUG, "new PxIE: 0x%08x.\n", reg32);
+
+ /* set PxSCTL.IPM (bit 8-11) to 3,
+ * disable transitions to PARTIAL and SLUMBER states
+ */
+ u8 *PxSCTL = port_control_reg+0x2c;
+ reg32 = read32(PxSCTL);
+ printk(BIOS_DEBUG, "changing PxSCTL: 0x%08x.\n", reg32);
+ reg32 |= 0x00000300;
+ write32(PxSCTL, reg32);
+ printk(BIOS_DEBUG, "new PxSCTL: 0x%08x.\n", reg32);
+
+ /* set PxCMD.ESP(bit 21), PxCMD.HPCP(bit 18), PxCMD.MPSP(bit 19) */
+ u8 *PxCMD = port_control_reg+0x18;
+ reg32 = read32(PxCMD);
+ printk(BIOS_DEBUG, "changing PxCMD: 0x%08x.\n", reg32);
+ reg32 |= 0x002c0000;
+ write32(PxCMD, reg32);
+ reg32 = read32(PxCMD);
+ printk(BIOS_DEBUG, "new PxCMD: 0x%08x.\n", reg32);
+ }
+ }
} else {
/* IDE */
printk(BIOS_DEBUG, "SATA: Controller in plain mode.\n");
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