[coreboot-gerrit] Patch set updated for coreboot: soc/intel/quark: Add C bootblock
Leroy P Leahy (leroy.p.leahy@intel.com)
gerrit at coreboot.org
Fri Jun 10 23:28:45 CEST 2016
Leroy P Leahy (leroy.p.leahy at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15132
-gerrit
commit 165606fa53d1df02bfda4fe2fb4553427f960a41
Author: Lee Leahy <leroy.p.leahy at intel.com>
Date: Sun Jun 5 18:48:31 2016 -0700
soc/intel/quark: Add C bootblock
Add a bootblock which builds with C_ENVIRONMENT_BOOTBLOCK selected.
This is the first piece in supporting FSP 2.0. Move esraminit from
romstage into the bootblock. Replace cache_as_ram with
car_stage_entry.S and code in romstage.c
TEST=Build and run on Galileo Gen2
Change-Id: I14d2af2adb6e75d4bff1ebfb863196df04d07daf
Signed-off-by: Lee Leahy <leroy.p.leahy at intel.com>
---
src/soc/intel/quark/Kconfig | 15 +
src/soc/intel/quark/Makefile.inc | 7 +
src/soc/intel/quark/bootblock/bootblock.c | 77 ++++
src/soc/intel/quark/bootblock/esram_init.S | 540 +++++++++++++++++++++++++
src/soc/intel/quark/include/soc/romstage.h | 1 +
src/soc/intel/quark/romstage/Makefile.inc | 4 +-
src/soc/intel/quark/romstage/cache_as_ram.inc | 252 ------------
src/soc/intel/quark/romstage/car_stage_entry.S | 75 ++++
src/soc/intel/quark/romstage/esram_init.inc | 516 -----------------------
src/soc/intel/quark/romstage/romstage.c | 28 ++
10 files changed, 744 insertions(+), 771 deletions(-)
diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig
index 2c7ec64..37b669d 100644
--- a/src/soc/intel/quark/Kconfig
+++ b/src/soc/intel/quark/Kconfig
@@ -26,6 +26,8 @@ config CPU_SPECIFIC_OPTIONS
select ARCH_RAMSTAGE_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_VERSTAGE_X86_32
+ select BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP
+ select C_ENVIRONMENT_BOOTBLOCK
select REG_SCRIPT
select SOC_INTEL_COMMON
select SOC_SETS_MTRRS
@@ -261,4 +263,17 @@ config RMU_LOC
The location in CBFS that the RMU is located. It must match the
strap-determined base address.
+#####
+# Bootblock
+# The following options support the C_ENVIRONMENT_BOOTBLOCK.
+#####
+
+config DCACHE_BSP_STACK_SIZE
+ hex
+ default 0x4000
+
+config C_ENV_BOOTBLOCK_SIZE
+ hex
+ default 0x8000
+
endif # SOC_INTEL_QUARK
diff --git a/src/soc/intel/quark/Makefile.inc b/src/soc/intel/quark/Makefile.inc
index d747079..edbb8be 100644
--- a/src/soc/intel/quark/Makefile.inc
+++ b/src/soc/intel/quark/Makefile.inc
@@ -18,6 +18,13 @@ ifeq ($(CONFIG_SOC_INTEL_QUARK),y)
subdirs-y += romstage
subdirs-y += ../../../cpu/x86/tsc
+bootblock-y += bootblock/esram_init.S
+bootblock-y += bootblock/bootblock.c
+bootblock-y += i2c.c
+bootblock-y += reg_access.c
+bootblock-y += tsc_freq.c
+bootblock-y += uart_common.c
+
romstage-y += i2c.c
romstage-y += memmap.c
romstage-y += reg_access.c
diff --git a/src/soc/intel/quark/bootblock/bootblock.c b/src/soc/intel/quark/bootblock/bootblock.c
new file mode 100644
index 0000000..669cd47
--- /dev/null
+++ b/src/soc/intel/quark/bootblock/bootblock.c
@@ -0,0 +1,77 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2015-2016 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#include <bootblock_common.h>
+#include <console/console.h>
+#include <device/pci_def.h>
+#include <program_loading.h>
+#include <soc/iomap.h>
+#include <soc/pci_devs.h>
+#include <soc/reg_access.h>
+
+static const struct reg_script clear_smi_and_wake_events[] = {
+ /* Clear any SMI or wake events */
+ REG_GPE0_READ(R_QNC_GPE0BLK_GPE0S),
+ REG_GPE0_READ(R_QNC_GPE0BLK_SMIS),
+ REG_GPE0_OR(R_QNC_GPE0BLK_GPE0S, B_QNC_GPE0BLK_GPE0S_ALL),
+ REG_GPE0_OR(R_QNC_GPE0BLK_SMIS, B_QNC_GPE0BLK_SMIS_ALL),
+ REG_SCRIPT_END
+};
+
+static const struct reg_script legacy_gpio_init[] = {
+ /* Temporarily enable the legacy GPIO controller */
+ REG_PCI_WRITE32(R_QNC_LPC_GBA_BASE, IO_ADDRESS_VALID
+ | LEGACY_GPIO_BASE_ADDRESS),
+ /* Temporarily enable the GPE controller */
+ REG_PCI_WRITE32(R_QNC_LPC_GPE0BLK, IO_ADDRESS_VALID
+ | GPE0_BASE_ADDRESS),
+ REG_PCI_OR8(PCI_COMMAND, PCI_COMMAND_IO),
+ REG_SCRIPT_END
+};
+
+static const struct reg_script i2c_gpio_controller_init[] = {
+ /* Temporarily enable the GPIO controller */
+ REG_PCI_WRITE32(PCI_BASE_ADDRESS_0, I2C_BASE_ADDRESS),
+ REG_PCI_WRITE32(PCI_BASE_ADDRESS_1, GPIO_BASE_ADDRESS),
+ REG_PCI_OR8(PCI_COMMAND, PCI_COMMAND_MEMORY),
+ REG_SCRIPT_END
+};
+
+static const struct reg_script hsuart_init[] = {
+ /* Enable the HSUART */
+ REG_PCI_WRITE32(PCI_BASE_ADDRESS_0, UART_BASE_ADDRESS),
+ REG_PCI_OR8(PCI_COMMAND, PCI_COMMAND_MEMORY),
+ REG_SCRIPT_END
+};
+
+void bootblock_soc_early_init(void)
+{
+ /* Initialize the controllers */
+ reg_script_run_on_dev(I2CGPIO_BDF, i2c_gpio_controller_init);
+ reg_script_run_on_dev(LPC_BDF, legacy_gpio_init);
+
+ /* Enable the HSUART */
+ if (IS_ENABLED(CONFIG_ENABLE_BUILTIN_HSUART0))
+ reg_script_run_on_dev(HSUART0_BDF, hsuart_init);
+ if (IS_ENABLED(CONFIG_ENABLE_BUILTIN_HSUART1))
+ reg_script_run_on_dev(HSUART1_BDF, hsuart_init);
+}
+
+void platform_prog_run(struct prog *prog)
+{
+ /* Display the program entry point */
+ printk(BIOS_SPEW, "Calling %s, 0x%p(0x%p)\n", prog->name,
+ prog->entry, prog->arg);
+}
diff --git a/src/soc/intel/quark/bootblock/esram_init.S b/src/soc/intel/quark/bootblock/esram_init.S
new file mode 100644
index 0000000..e309ca4
--- /dev/null
+++ b/src/soc/intel/quark/bootblock/esram_init.S
@@ -0,0 +1,540 @@
+/** @file
+ *
+ * Copyright (C) 2015-2016, Intel Corporation
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * * Neither the name of Intel Corporation nor the names of its contributors may
+ * be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ *
+**/
+
+#include <cpu/x86/cr.h>
+#include <cpu/x86/post_code.h>
+#include <soc/QuarkNcSocId.h>
+
+.macro RET32
+ jmp *%esp
+.endm
+
+/* ROM/SPI/MEMORY Definitions */
+.equ QUARK_DDR3_MEM_BASE_ADDRESS, (0x000000000) /* Memory Base Address = 0 */
+.equ QUARK_MAX_DDR3_MEM_SIZE_BYTES, (0x80000000) /* DDR3 Memory Size = 2GB */
+.equ QUARK_ESRAM_MEM_BASE_ADDRESS, (QUARK_DDR3_MEM_BASE_ADDRESS \
+ + QUARK_MAX_DDR3_MEM_SIZE_BYTES) /* eSRAM Memory above DDR3 */
+.equ QUARK_ESRAM_MEM_SIZE_BYTES, (0x00080000) /* eSRAM Memory Size = 512K */
+.equ QUARK_STACK_SIZE_BYTES, (0x008000) /* Quark stack size = 32K */
+.equ QUARK_STACK_BASE_ADDRESS, (QUARK_ESRAM_MEM_BASE_ADDRESS \
+ + QUARK_ESRAM_MEM_SIZE_BYTES \
+ - QUARK_STACK_SIZE_BYTES) /* Top of eSRAM - stack size */
+.equ QUARK_CMH_SIZE_BYTES, (0x0400) /* Quark Module Header size */
+.equ QUARK_ESRAM_STAGE1_BASE_ADDRESS, (QUARK_ESRAM_MEM_BASE_ADDRESS \
+ + QUARK_CMH_SIZE_BYTES) /* Start of Stage1 code in eSRAM */
+
+/* RTC/CMOS definitions */
+.equ RTC_INDEX, (0x70)
+.equ NMI_DISABLE, (0x80) /* Bit7=1 disables NMI */
+.equ RTC_DATA, (0x71)
+
+/* PCI Configuration definitions (Datasheet 5.5.1) */
+.equ PCI_CFG, (0x80000000) /* PCI configuration access mechanism */
+.equ PCI_ADDRESS_PORT, (0xCF8)
+.equ PCI_DATA_PORT, (0xCFC)
+
+/* Quark PCI devices */
+.equ HOST_BRIDGE_PFA, (0 << 11) /* B0:D0:F0 (Host Bridge) */
+.equ ILB_PFA, (0x1F << 11) /* B0:D31:F0 (Legacy Block) */
+
+/* ILB PCI Config Registers */
+.equ BDE, (0x0D4) /* BIOS Decode Enable register */
+.equ DECODE_ALL_REGIONS_ENABLE, (0xFF000000) /* Decode all BIOS ranges */
+
+/* iLB Reset Register */
+.equ ILB_RESET_REG, (0x0CF9)
+.equ CF9_WARM_RESET, (0x02)
+.equ CF9_COLD_RESET, (0x08)
+
+/* Memory Arbiter Config Registers */
+.equ AEC_CTRL_OFFSET, (0x00)
+
+/* Host Bridge Config Registers */
+.equ HMBOUND_OFFSET, (0x08)
+.equ HMBOUND_ADDRESS, (QUARK_DDR3_MEM_BASE_ADDRESS \
+ + QUARK_MAX_DDR3_MEM_SIZE_BYTES + QUARK_ESRAM_MEM_SIZE_BYTES)
+.equ HECREG_OFFSET, (0x09)
+.equ EC_BASE, (0xE0000000)
+.equ EC_ENABLE, (0x01)
+
+/* Memory Manager Config Registers */
+.equ ESRAM_ADDRESS_2G, (0x10000080)
+.equ BIMRVCTL_OFFSET, (0x19)
+.equ ENABLE_IMR_INTERRUPT, (0x80000000)
+
+/* SOC UNIT Debug Registers */
+.equ CFGSTICKY_W1_OFFSET, (0x50)
+.equ FORCE_COLD_RESET, (0x00000001)
+.equ CFGSTICKY_RW_OFFSET, (0x51)
+.equ RESET_FOR_ESRAM_LOCK, (0x00000020)
+.equ RESET_FOR_HMBOUND_LOCK, (0x00000040)
+.equ CFGNONSTICKY_W1_OFFSET, (0x52)
+.equ FORCE_WARM_RESET, (0x00000001)
+
+ .global bootblock_save_bist_and_timestamp
+
+bootblock_save_bist_and_timestamp:
+
+ /* eax: Low 32-bits of timestamp
+ * ebx: BIST result
+ * ebp: return address
+ * edx: High 32-bits of timestamp
+ */
+
+ /* No value to save since Quark does not generate a BIST value
+ * Save the timestamp in edi:ebp
+ */
+ xchgl %eax, %ebp
+ movl %edx, %edi
+ jmp *%eax
+
+ .global bootblock_pre_c_entry
+
+bootblock_pre_c_entry:
+
+ /* Registers:
+ * ebp: Low 32-bits of timestamp
+ * edi: High 32-bits of timestamp
+ */
+
+setup_esram:
+ /* Ensure cache is disabled. */
+ movl %cr0, %eax
+ orl $(CR0_CD | CR0_NW), %eax
+ invd
+ movl %eax, %cr0
+
+ /*
+ * Disable NMI operation
+ * Good convention suggests you should read back RTC data port after
+ * accessing the RTC index port.
+ */
+ movb $(NMI_DISABLE), %al
+ movw $(RTC_INDEX), %dx
+ outb %al, %dx
+ movw $(RTC_DATA), %dx
+ inb %dx, %al
+
+ /* Disable SMI (Disables SMI wire, not SMI messages) */
+ movl $((QUARK_OPCODE_READ << QNC_MCR_OP_OFFSET) \
+ | (QUARK_NC_HOST_BRIDGE_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \
+ | (QNC_MSG_FSBIC_REG_HMISC << QNC_MCR_REG_OFFSET)), %ecx
+ leal L1, %esp
+ jmp stackless_SideBand_Read
+L1:
+ andl $(~SMI_EN), %eax
+ movl $((QUARK_OPCODE_WRITE << QNC_MCR_OP_OFFSET) \
+ | (QUARK_NC_HOST_BRIDGE_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \
+ | (QNC_MSG_FSBIC_REG_HMISC << QNC_MCR_REG_OFFSET)), %ecx
+ leal L2, %esp
+ jmp stackless_SideBand_Write
+L2:
+
+ /*
+ * Before we get going, check SOC Unit Registers to see if we are
+ * required to issue a warm/cold reset
+ */
+ movl $((QUARK_ALT_OPCODE_READ << QNC_MCR_OP_OFFSET) \
+ | (QUARK_SCSS_SOC_UNIT_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \
+ | (CFGNONSTICKY_W1_OFFSET << QNC_MCR_REG_OFFSET)), %ecx
+ leal L3, %esp
+ jmp stackless_SideBand_Read
+L3:
+ andl $(FORCE_WARM_RESET), %eax
+ jz TestForceColdReset /* No warm reset - branch */
+ jmp IssueWarmReset
+
+TestForceColdReset:
+ movl $((QUARK_ALT_OPCODE_READ << QNC_MCR_OP_OFFSET) \
+ | (QUARK_SCSS_SOC_UNIT_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \
+ | (CFGNONSTICKY_W1_OFFSET << QNC_MCR_REG_OFFSET)), %ecx
+ leal L4, %esp
+ jmp stackless_SideBand_Read
+L4:
+ andl $(FORCE_COLD_RESET), %eax
+ jz TestHmboundLock /* No cold reset - branch */
+ jmp IssueColdReset
+
+ /* Before setting HMBOUND, check it's not locked */
+TestHmboundLock:
+ movl $((QUARK_OPCODE_READ << QNC_MCR_OP_OFFSET) \
+ | (QUARK_NC_HOST_BRIDGE_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \
+ | (HMBOUND_OFFSET << QNC_MCR_REG_OFFSET)), %ecx
+ leal L5, %esp
+ jmp stackless_SideBand_Read
+L5:
+ andl $(HMBOUND_LOCK), %eax
+ jz ConfigHmbound /* Good configuration - branch */
+
+ /* Failed to config - store sticky bit debug */
+ movl $((QUARK_ALT_OPCODE_READ << QNC_MCR_OP_OFFSET) \
+ | (QUARK_SCSS_SOC_UNIT_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \
+ | (CFGSTICKY_RW_OFFSET << QNC_MCR_REG_OFFSET)), %ecx
+ leal L6, %esp
+ jmp stackless_SideBand_Read
+L6:
+ orl $(RESET_FOR_HMBOUND_LOCK), %eax
+ movl $((QUARK_ALT_OPCODE_WRITE << QNC_MCR_OP_OFFSET) \
+ | (QUARK_SCSS_SOC_UNIT_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \
+ | (CFGSTICKY_RW_OFFSET << QNC_MCR_REG_OFFSET)), %ecx
+ leal L7, %esp
+ jmp stackless_SideBand_Write
+L7:
+ jmp IssueWarmReset
+
+ /* Set up the HMBOUND register */
+ConfigHmbound:
+ movl $(HMBOUND_ADDRESS), %eax /* Data (Set HMBOUND location) */
+ movl $((QUARK_OPCODE_WRITE << QNC_MCR_OP_OFFSET) \
+ | (QUARK_NC_HOST_BRIDGE_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \
+ | (HMBOUND_OFFSET << QNC_MCR_REG_OFFSET)), %ecx
+ leal L8, %esp
+ jmp stackless_SideBand_Write
+L8:
+
+ /*
+ * Enable interrupts to Remote Management Unit when a IMR/SMM/HMBOUND
+ * violation occurs.
+ */
+ movl $(ENABLE_IMR_INTERRUPT), %eax /* Set interrupt enable mask */
+ movl $((QUARK_OPCODE_WRITE << QNC_MCR_OP_OFFSET) \
+ | (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \
+ | (BIMRVCTL_OFFSET << QNC_MCR_REG_OFFSET)), %ecx
+ leal L9, %esp
+ jmp stackless_SideBand_Write
+L9:
+
+ /* Move eSRAM memory to 2GB */
+ movl $(ESRAM_ADDRESS_2G), %eax /* Data (Set eSRAM location) */
+ movl $((QUARK_OPCODE_WRITE << QNC_MCR_OP_OFFSET) \
+ | (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \
+ | (QUARK_NC_MEMORY_MANAGER_ESRAMPGCTRL_BLOCK \
+ << QNC_MCR_REG_OFFSET)), %ecx
+ leal L10, %esp
+ jmp stackless_SideBand_Write
+L10:
+
+ /* Check that we're not blocked from setting the config that we want. */
+ movl $((QUARK_OPCODE_READ << QNC_MCR_OP_OFFSET) \
+ | (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \
+ | (QUARK_NC_MEMORY_MANAGER_ESRAMPGCTRL_BLOCK \
+ << QNC_MCR_REG_OFFSET)), %ecx
+ leal L11, %esp
+ jmp stackless_SideBand_Read
+L11:
+ andl $(BLOCK_ENABLE_PG), %eax
+ jnz ConfigPci /* Good configuration - branch */
+
+ /* Failed to config - store sticky bit debug */
+ movl $((QUARK_ALT_OPCODE_READ << QNC_MCR_OP_OFFSET) \
+ | (QUARK_SCSS_SOC_UNIT_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \
+ | (CFGSTICKY_RW_OFFSET << QNC_MCR_REG_OFFSET)), %ecx
+ leal L12, %esp
+ jmp stackless_SideBand_Read
+L12:
+ orl $(RESET_FOR_ESRAM_LOCK), %eax
+ movl $((QUARK_ALT_OPCODE_WRITE << QNC_MCR_OP_OFFSET) \
+ | (QUARK_SCSS_SOC_UNIT_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \
+ | (CFGSTICKY_RW_OFFSET << QNC_MCR_REG_OFFSET)), %ecx
+ leal L13, %esp
+ jmp stackless_SideBand_Write
+L13:
+ jmp IssueWarmReset
+
+ /* Enable PCIEXBAR */
+ConfigPci:
+ movl $(EC_BASE + EC_ENABLE), %eax /* Data */
+ movl $((QUARK_OPCODE_WRITE << QNC_MCR_OP_OFFSET) \
+ | (QUARK_NC_MEMORY_ARBITER_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \
+ | (AEC_CTRL_OFFSET << QNC_MCR_REG_OFFSET)), %ecx
+ leal L14, %esp
+ jmp stackless_SideBand_Write
+L14:
+
+ movl $(EC_BASE + EC_ENABLE), %eax /* Data */
+ movl $((QUARK_OPCODE_WRITE << QNC_MCR_OP_OFFSET) \
+ | (QUARK_NC_HOST_BRIDGE_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \
+ | (HECREG_OFFSET << QNC_MCR_REG_OFFSET)), %ecx
+ leal L15, %esp
+ jmp stackless_SideBand_Write
+L15:
+
+ /* Open up full 8MB SPI decode */
+ movl $(PCI_CFG | ILB_PFA | BDE), %ebx /* PCI config address */
+ movl $(DECODE_ALL_REGIONS_ENABLE), %eax
+ leal L16, %esp
+ jmp stackless_PCIConfig_Write
+L16:
+
+ jmp esram_init_done
+
+IssueWarmReset:
+ /* Issue Warm Reset request to Remote Management Unit via iLB */
+ movw $(CF9_WARM_RESET), %ax
+ movw $(ILB_RESET_REG), %dx
+ outw %ax, %dx
+ jmp . /* Stay here until we are reset. */
+
+IssueColdReset:
+ /* Issue Cold Reset request to Remote Management Unit via iLB */
+ movw $(CF9_COLD_RESET), %ax
+ movw $(ILB_RESET_REG), %dx
+ outw %ax, %dx
+ jmp . /* Stay here until we are reset. */
+
+/*
+ *----------------------------------------------------------------------------
+ *
+ * Procedure: stackless_SideBand_Read
+ *
+ * Input: esp - return address
+ * ecx[15:8] - Register offset
+ * ecx[23:16] - Port ID
+ * ecx[31:24] - Opcode
+ *
+ * Output: eax - Data read
+ *
+ * Destroys: eax
+ * ebx
+ * cl
+ * esi
+ *
+ * Description:
+ * Perform requested sideband read
+ *----------------------------------------------------------------------------
+ */
+
+stackless_SideBand_Read:
+
+ movl %esp, %esi /* Save the return address */
+
+ /* Load the SideBand Packet Register to generate the transaction */
+ movl $(PCI_CFG | HOST_BRIDGE_PFA | QNC_ACCESS_PORT_MCR), %ebx
+ movb $QNC_MCR_BYTE_ENABLES, %cl /* Set all Byte Enable bits */
+ xchgl %ecx, %eax
+ leal L17, %esp
+ jmp stackless_PCIConfig_Write
+L17:
+ xchgl %ecx, %eax
+
+ /* Read the SideBand Data Register */
+ movl $(PCI_CFG | HOST_BRIDGE_PFA | (QNC_ACCESS_PORT_MDR)), %ebx
+ leal L18, %esp
+ jmp stackless_PCIConfig_Read
+L18:
+
+ movl %esi, %esp /* Restore the return address */
+ RET32
+
+/*
+ *----------------------------------------------------------------------------
+ *
+ * Procedure: stackless_SideBand_Write
+ *
+ * Input: esp - return address
+ * eax - Data
+ * ecx[15:8] - Register offset
+ * ecx[23:16] - Port ID
+ * ecx[31:24] - Opcode
+ *
+ * Output: None
+ *
+ * Destroys: ebx
+ * cl
+ * esi
+ *
+ * Description:
+ * Perform requested sideband write
+ *
+ *----------------------------------------------------------------------------
+ */
+
+stackless_SideBand_Write:
+
+ movl %esp, %esi /* Save the return address */
+
+ /* Load the SideBand Data Register with the data */
+ movl $(PCI_CFG | HOST_BRIDGE_PFA | QNC_ACCESS_PORT_MDR), %ebx
+ leal L19, %esp
+ jmp stackless_PCIConfig_Write
+L19:
+
+ /* Load the SideBand Packet Register to generate the transaction */
+ movl $(PCI_CFG | HOST_BRIDGE_PFA | QNC_ACCESS_PORT_MCR), %ebx
+ movb $QNC_MCR_BYTE_ENABLES, %cl /* Set all Byte Enable bits */
+ xchgl %ecx, %eax
+ leal L20, %esp
+ jmp stackless_PCIConfig_Write
+L20:
+ xchgl %ecx, %eax
+
+ movl %esi, %esp /* Restore the return address */
+ RET32
+
+/*
+ *----------------------------------------------------------------------------
+ *
+ * Procedure: stackless_PCIConfig_Write
+ *
+ * Input: esp - return address
+ * eax - Data to write
+ * ebx - PCI Config Address
+ *
+ * Output: None
+ *
+ * Destroys: dx
+ *
+ * Description:
+ * Perform a DWORD PCI Configuration write
+ *
+ *----------------------------------------------------------------------------
+ */
+
+stackless_PCIConfig_Write:
+
+ /* Write the PCI Config Address to the address port */
+ xchgl %ebx, %eax
+ movw $(PCI_ADDRESS_PORT), %dx
+ outl %eax, %dx
+ xchgl %ebx, %eax
+
+ /* Write the PCI DWORD Data to the data port */
+ movw $(PCI_DATA_PORT), %dx
+ outl %eax, %dx
+
+ RET32
+
+/*
+ *----------------------------------------------------------------------------
+ *
+ * Procedure: stackless_PCIConfig_Read
+ *
+ * Input: esp - return address
+ * ebx - PCI Config Address
+ *
+ * Output: eax - Data read
+ *
+ * Destroys: eax
+ * dx
+ *
+ * Description:
+ * Perform a DWORD PCI Configuration read
+ *
+ *----------------------------------------------------------------------------
+ */
+
+stackless_PCIConfig_Read:
+
+ /* Write the PCI Config Address to the address port */
+ xchgl %ebx, %eax
+ movw $(PCI_ADDRESS_PORT), %dx
+ outl %eax, %dx
+ xchgl %ebx, %eax
+
+ /* Read the PCI DWORD Data from the data port */
+ movw $(PCI_DATA_PORT), %dx
+ inl %dx, %eax
+
+ RET32
+
+/*----------------------------------------------------------------------------*/
+
+esram_init_done:
+
+#if IS_ENABLED(CONFIG_ENABLE_DEBUG_LED)
+sd_led:
+
+.equ SD_PFA, (0x14 << 11) /* B0:D20:F0 - SDIO controller */
+.equ SD_CFG_BASE, (PCI_CFG | SD_PFA) /* SD cntrl base in PCI config space */
+.equ SD_CFG_CMD, (SD_CFG_BASE+0x04) /* Command reg in PCI config space */
+.equ SD_CFG_ADDR, (SD_CFG_BASE+0x10) /* Base address in PCI config space */
+.equ SD_BASE_ADDR, (0xA0018000) /* SD controller's base address */
+.equ SD_HOST_CTRL, (SD_BASE_ADDR+0x28) /* HOST_CTRL register */
+
+ /* Set the SDIO controller's base address */
+ movl $(SD_BASE_ADDR), %eax
+ movl $(SD_CFG_ADDR), %ebx
+ leal L40, %esp
+ jmp stackless_PCIConfig_Write
+
+L40:
+ movl $(SD_CFG_ADDR), %ebx
+ leal L41, %esp
+ jmp stackless_PCIConfig_Read
+
+L41:
+ /* Enable the SDIO controller */
+ movl $(SD_CFG_CMD), %ebx
+ leal L42, %esp
+ jmp stackless_PCIConfig_Read
+
+L42:
+ orl $2, %eax
+ movl $(SD_CFG_CMD), %ebx
+ leal L43, %esp
+ jmp stackless_PCIConfig_Write
+
+L43:
+ movl $(SD_CFG_CMD), %ebx
+ leal L44, %esp
+ jmp stackless_PCIConfig_Read
+
+L44:
+#if IS_ENABLED(CONFIG_ENABLE_DEBUG_LED_ESRAM)
+ /* Turn on SD LED to indicate ESRAM successfully initialized */
+ movl $SD_HOST_CTRL, %ebx
+ movb 0(%ebx), %al
+ orb $1, %al
+ movb %al, 0(%ebx)
+
+ /* Loop forever */
+ jmp .
+#endif /* CONFIG_ENABLE_DEBUG_LED_ESRAM */
+#endif /* CONFIG_ENABLE_DEBUG_LED */
+
+ /* Registers:
+ * ebp: Low 32-bits of timestamp
+ * edi: High 32-bits of timestamp
+ */
+
+ /* Setup bootblock stack */
+ movl $_car_stack_end, %esp
+
+before_carstage:
+ post_code(0x2b)
+
+ /* Restore the timestamp from bootblock_crt0.S (mm2:mm1) */
+ push %ebp
+ push %edi
+
+ /* We can call into C functions now */
+ call bootblock_main_with_timestamp
+
+ /* Never reached */
diff --git a/src/soc/intel/quark/include/soc/romstage.h b/src/soc/intel/quark/include/soc/romstage.h
index 3a9e7a8..47545ac 100644
--- a/src/soc/intel/quark/include/soc/romstage.h
+++ b/src/soc/intel/quark/include/soc/romstage.h
@@ -25,6 +25,7 @@
#include <fsp/romstage.h>
#include <soc/reg_access.h>
+asmlinkage void *car_state_c_entry(void);
uint32_t port_reg_read(uint8_t port, uint32_t offset);
void port_reg_write(uint8_t port, uint32_t offset, uint32_t value);
void report_platform_info(void);
diff --git a/src/soc/intel/quark/romstage/Makefile.inc b/src/soc/intel/quark/romstage/Makefile.inc
index 6c92ac4..16fc5ac 100644
--- a/src/soc/intel/quark/romstage/Makefile.inc
+++ b/src/soc/intel/quark/romstage/Makefile.inc
@@ -13,9 +13,7 @@
# GNU General Public License for more details.
#
-cpu_incs-y += $(src)/soc/intel/quark/romstage/esram_init.inc
-cpu_incs-y += $(src)/soc/intel/quark/romstage/cache_as_ram.inc
-
+romstage-y += car_stage_entry.S
romstage-y += mtrr.c
romstage-y += pcie.c
romstage-y += report_platform.c
diff --git a/src/soc/intel/quark/romstage/cache_as_ram.inc b/src/soc/intel/quark/romstage/cache_as_ram.inc
deleted file mode 100644
index a935bdf..0000000
--- a/src/soc/intel/quark/romstage/cache_as_ram.inc
+++ /dev/null
@@ -1,252 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich at gmail.com>
- * Copyright (C) 2007-2008 coresystems GmbH
- * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
- * Copyright (C) 2015-2016 Intel Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/*
- * Replacement for cache_as_ram.inc when using the FSP binary. This code
- * locates the FSP binary, initializes the cache as RAM and performs the
- * first stage of initialization. Next this code switches the stack from
- * the cache to RAM and then disables the cache as RAM. Finally this code
- * performs the final stage of initialization.
- */
-
-#include <rules.h>
-
- /*
- * eax: BIST value
- */
-
- movl %eax, %edi
-
-cache_as_ram:
- post_code(0x20)
-
- /*
- * edi: BIST value
- */
-
- /*
- * Find the FSP binary in cbfs.
- * Make a fake stack that has the return value back to this code.
- */
- lea fake_fsp_stack, %esp
- jmp find_fsp
-
-find_fsp_ret:
- /* Save the FSP location */
- mov %eax, %ebp
-
- /*
- * Only when a valid FSP binary is found at CONFIG_FSP_LOC is
- * the returned FSP_INFO_HEADER structure address above the base
- * address of FSP binary specified by the CONFIG_FSP_LOC value.
- * All of the error values are in the 0x8xxxxxxx range which are
- * below the CONFIG_FSP_LOC value.
- */
- cmp $CONFIG_FSP_ESRAM_LOC, %eax
- jbe halt1
-
- post_code(POST_FSP_TEMP_RAM_INIT)
-
-#if IS_ENABLED(CONFIG_ENABLE_DEBUG_LED_FINDFSP)
- movl $SD_HOST_CTRL, %ebx
- movb 0(%ebx), %al
- orb $1, %al
- movb %al, 0(%ebx)
- jmp .
-#endif /* CONFIG_ENABLE_DEBUG_LED_FINDFSP */
-
- /* Calculate entry into FSP */
- mov 0x30(%ebp), %eax /* Load TempRamInitEntry */
- add 0x1c(%ebp), %eax /* add in the offset for FSP */
-
- /*
- * Pass early init variables on a fake stack (no memory yet)
- * as well as the return location
- */
- lea CAR_init_stack, %esp
-
- /*
- * BIST value is zero
- * eax: TempRamInitApi address
- * ebp: FSP_INFO_HEADER address
- * edi: BIST value
- * esi: Not used
- */
-
- /* call FSP binary to setup temporary stack */
- jmp *%eax
-
-CAR_init_done:
- addl $4, %esp
-
- /*
- * ebp: FSP_INFO_HEADER address
- * ecx: Temp RAM base
- * edx: Temp RAM top
- * edi: BIST value
- */
-
- cmp $0, %eax
- jne halt2
-
-#if IS_ENABLED(CONFIG_ENABLE_DEBUG_LED_TEMPRAMINIT)
- movl %edx, %esi
- movl $SD_HOST_CTRL, %ebx
- movb 0(%ebx), %al
- orb $1, %al
- movb %al, 0(%ebx)
- movl %esi, %edx
- jmp .
-#endif /* CONFIG_ENABLE_DEBUG_LED_TEMPRAMINIT */
-
- /* Set up bootloader stack */
- movl %edx, %esp
-
- /*
- * eax: 0
- * ebp: FSP_INFO_HEADER address
- * ecx: Temp RAM base
- * edx: Temp RAM top
- * edi: BIST value
- * esp: Top of stack in temp RAM
- */
-
- /* Create cache_as_ram_params on stack */
- pushl %edx /* bootloader CAR end */
- pushl %ecx /* bootloader CAR begin */
- pushl %ebp /* FSP_INFO_HEADER */
- pushl $0 /* BIST - esram_init.inc catches non-zero BIST values */
- /* TODO: Locate 64-bits of storage for initial TSC value */
- pushl $0 /* tsc[63:32] */
- pushl $0 /* tsc[31:0] */
- pushl %esp /* pointer to cache_as_ram_params */
-
- /* Save FSP_INFO_HEADER location in ebx */
- mov %ebp, %ebx
-
- /* Coreboot assumes stack/heap region will be zero */
- cld
- movl %ecx, %edi
- neg %ecx
- /* Only clear up to current stack value. */
- add %esp, %ecx
- shrl $2, %ecx
- xorl %eax, %eax
- rep stosl
-
-before_romstage:
- post_code(0x2A)
-
- /* Call cache_as_ram_main(struct cache_as_ram_params *) */
- call cache_as_ram_main
-
-/* One will never return from cache_as_ram_main() in verstage so there's
- * no such thing as after ram init. */
-#if !ENV_VERSTAGE
-#include "src/drivers/intel/fsp1_1/after_raminit.S"
-#endif
-
- movb $0x69, %ah
- jmp .Lhlt
-
-halt1:
- /*
- * Failures for postcode 0xBA - failed in fsp_fih_early_find()
- *
- * Values are:
- * 0x01 - FV signature, "_FVH" not present
- * 0x02 - FFS GUID not present
- * 0x03 - FSP INFO Header not found
- * 0x04 - ImageBase does not equal CONFIG_FSP_LOC - Is the FSP rebased to
- * a different location, or does it need to be?
- * 0x05 - FSP INFO Header signature "FSPH" not found
- * 0x06 - FSP Image ID is not the expected ID.
- */
- movb $0xBA, %ah
- jmp .Lhlt
-
-halt2:
- /*
- * Failures for postcode 0xBB - failed in the FSP:
- *
- * 0x00 - FSP_SUCCESS: Temp RAM was initialized successfully.
- * 0x02 - FSP_INVALID_PARAMETER: Input parameters are invalid.
- * 0x03 - FSP_UNSUPPORTED: The FSP calling conditions were not met.
- * 0x07 - FSP_DEVICE_ERROR: Temp RAM initialization failed
- * 0x0E - FSP_NOT_FOUND: No valid microcode was found in the microcode region.
- * 0x14 - FSP_ALREADY_STARTED: Temp RAM initialization has been invoked
- */
- movb $0xBB, %ah
- jmp .Lhlt
-
-#----------------------------------------------------------------------------
-#
-# Procedure: .Lhlt
-#
-# Input: ah - Upper 8-bits of POST code
-# al - Lower 8-bits of POST code
-#
-# Description:
-# Infinite loop displaying alternating POST code values
-#
-#----------------------------------------------------------------------------
-
-#define FLASH_DELAY 0x1000 /* I/O delay between post codes on failure */
-#define POST_DELAY 0x50
-
-.Lhlt:
- xchg %al, %ah
- mov $POST_DELAY, %dh
-#if IS_ENABLED(CONFIG_POST_IO)
- outb %al, $CONFIG_POST_IO_PORT
-#else
- post_code(POST_DEAD_CODE)
-#endif
-.flash_setup:
- movl $FLASH_DELAY, %ecx
-.flash_delay:
- outb %al, $0xED
- loop .flash_delay
-#if IS_ENABLED(CONFIG_ENABLE_DEBUG_LED_FINDFSP)
- movl $SD_HOST_CTRL, %ebx
- movb 0(%ebx), %dl
- xorb $1, %dl
- movb %dl, 0(%ebx)
-#endif /* CONFIG_ENABLE_DEBUG_LED_FINDFSP */
- decb %dh
- jnz .flash_setup
- jmp .Lhlt
-
-/*
- * esp is set to this location so that the call into and return from the FSP
- * in find_fsp will work.
- */
- .align 4
-fake_fsp_stack:
- .long find_fsp_ret
- .long CONFIG_FSP_ESRAM_LOC /* FSP base address */
-
-CAR_init_params:
- .long CONFIG_CPU_MICROCODE_CBFS_LOC /* Microcode Location */
- .long CONFIG_CPU_MICROCODE_CBFS_LEN /* Microcode Length */
- .long 0xFFFFFFFF - CONFIG_ROM_SIZE + 1 /* Firmware Location */
- .long CONFIG_ROM_SIZE /* Total Firmware Length */
-
-CAR_init_stack:
- .long CAR_init_done
- .long CAR_init_params
diff --git a/src/soc/intel/quark/romstage/car_stage_entry.S b/src/soc/intel/quark/romstage/car_stage_entry.S
new file mode 100644
index 0000000..be9426d
--- /dev/null
+++ b/src/soc/intel/quark/romstage/car_stage_entry.S
@@ -0,0 +1,75 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich at gmail.com>
+ * Copyright (C) 2007-2008 coresystems GmbH
+ * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
+ * Copyright (C) 2015-2016 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Replacement for cache_as_ram.inc when using the C environment boot block.
+ */
+
+#include <rules.h>
+
+ .section ".text"
+ .global car_stage_entry
+
+car_stage_entry:
+
+ /* Enter the C code */
+ call car_state_c_entry
+
+#if !ENV_VERSTAGE
+#include "src/drivers/intel/fsp1_1/after_raminit.S"
+#endif
+
+ /* The code should never reach this point */
+ movb $0x69, %ah
+ jmp .Lhlt
+
+#----------------------------------------------------------------------------
+#
+# Procedure: .Lhlt
+#
+# Input: ah - Upper 8-bits of POST code
+# al - Lower 8-bits of POST code
+#
+# Description:
+# Infinite loop displaying alternating POST code values
+#
+#----------------------------------------------------------------------------
+
+#define FLASH_DELAY 0x1000 /* I/O delay between post codes on failure */
+#define POST_DELAY 0x50
+
+.Lhlt:
+ xchg %al, %ah
+ mov $POST_DELAY, %dh
+#if IS_ENABLED(CONFIG_POST_IO)
+ outb %al, $CONFIG_POST_IO_PORT
+#else
+ post_code(POST_DEAD_CODE)
+#endif
+.flash_setup:
+ movl $FLASH_DELAY, %ecx
+.flash_delay:
+ outb %al, $0xED
+ loop .flash_delay
+#if IS_ENABLED(CONFIG_ENABLE_DEBUG_LED)
+ movl $SD_HOST_CTRL, %ebx
+ movb 0(%ebx), %dl
+ xorb $1, %dl
+ movb %dl, 0(%ebx)
+#endif /* CONFIG_ENABLE_DEBUG_LED */
+ decb %dh
+ jnz .flash_setup
+ jmp .Lhlt
diff --git a/src/soc/intel/quark/romstage/esram_init.inc b/src/soc/intel/quark/romstage/esram_init.inc
deleted file mode 100644
index b899741..0000000
--- a/src/soc/intel/quark/romstage/esram_init.inc
+++ /dev/null
@@ -1,516 +0,0 @@
-/** @file
- *
- * Copyright (C) 2015-2016, Intel Corporation
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * * Redistributions of source code must retain the above copyright notice, this
- * list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * * Neither the name of Intel Corporation nor the names of its contributors may
- * be used to endorse or promote products derived from this software without
- * specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
- * THE POSSIBILITY OF SUCH DAMAGE.
- *
-**/
-
-#include <cpu/x86/cr.h>
-#include <soc/QuarkNcSocId.h>
-
-.macro RET32
- jmp *%esp
-.endm
-
-/* ROM/SPI/MEMORY Definitions */
-.equ QUARK_DDR3_MEM_BASE_ADDRESS, (0x000000000) /* Memory Base Address = 0 */
-.equ QUARK_MAX_DDR3_MEM_SIZE_BYTES, (0x80000000) /* DDR3 Memory Size = 2GB */
-.equ QUARK_ESRAM_MEM_BASE_ADDRESS, (QUARK_DDR3_MEM_BASE_ADDRESS \
- + QUARK_MAX_DDR3_MEM_SIZE_BYTES) /* eSRAM Memory above DDR3 */
-.equ QUARK_ESRAM_MEM_SIZE_BYTES, (0x00080000) /* eSRAM Memory Size = 512K */
-.equ QUARK_STACK_SIZE_BYTES, (0x008000) /* Quark stack size = 32K */
-.equ QUARK_STACK_BASE_ADDRESS, (QUARK_ESRAM_MEM_BASE_ADDRESS \
- + QUARK_ESRAM_MEM_SIZE_BYTES \
- - QUARK_STACK_SIZE_BYTES) /* Top of eSRAM - stack size */
-.equ QUARK_CMH_SIZE_BYTES, (0x0400) /* Quark Module Header size */
-.equ QUARK_ESRAM_STAGE1_BASE_ADDRESS, (QUARK_ESRAM_MEM_BASE_ADDRESS \
- + QUARK_CMH_SIZE_BYTES) /* Start of Stage1 code in eSRAM */
-
-/* RTC/CMOS definitions */
-.equ RTC_INDEX, (0x70)
-.equ NMI_DISABLE, (0x80) /* Bit7=1 disables NMI */
-.equ RTC_DATA, (0x71)
-
-/* PCI Configuration definitions (Datasheet 5.5.1) */
-.equ PCI_CFG, (0x80000000) /* PCI configuration access mechanism */
-.equ PCI_ADDRESS_PORT, (0xCF8)
-.equ PCI_DATA_PORT, (0xCFC)
-
-/* Quark PCI devices */
-.equ HOST_BRIDGE_PFA, (0 << 11) /* B0:D0:F0 (Host Bridge) */
-.equ ILB_PFA, (0x1F << 11) /* B0:D31:F0 (Legacy Block) */
-
-/* ILB PCI Config Registers */
-.equ BDE, (0x0D4) /* BIOS Decode Enable register */
-.equ DECODE_ALL_REGIONS_ENABLE, (0xFF000000) /* Decode all BIOS ranges */
-
-/* iLB Reset Register */
-.equ ILB_RESET_REG, (0x0CF9)
-.equ CF9_WARM_RESET, (0x02)
-.equ CF9_COLD_RESET, (0x08)
-
-/* Memory Arbiter Config Registers */
-.equ AEC_CTRL_OFFSET, (0x00)
-
-/* Host Bridge Config Registers */
-.equ HMBOUND_OFFSET, (0x08)
-.equ HMBOUND_ADDRESS, (QUARK_DDR3_MEM_BASE_ADDRESS \
- + QUARK_MAX_DDR3_MEM_SIZE_BYTES + QUARK_ESRAM_MEM_SIZE_BYTES)
-.equ HECREG_OFFSET, (0x09)
-.equ EC_BASE, (0xE0000000)
-.equ EC_ENABLE, (0x01)
-
-/* Memory Manager Config Registers */
-.equ ESRAM_ADDRESS_2G, (0x10000080)
-.equ BIMRVCTL_OFFSET, (0x19)
-.equ ENABLE_IMR_INTERRUPT, (0x80000000)
-
-/* SOC UNIT Debug Registers */
-.equ CFGSTICKY_W1_OFFSET, (0x50)
-.equ FORCE_COLD_RESET, (0x00000001)
-.equ CFGSTICKY_RW_OFFSET, (0x51)
-.equ RESET_FOR_ESRAM_LOCK, (0x00000020)
-.equ RESET_FOR_HMBOUND_LOCK, (0x00000040)
-.equ CFGNONSTICKY_W1_OFFSET, (0x52)
-.equ FORCE_WARM_RESET, (0x00000001)
-
-verify_bist:
- cmp $0, %eax
- je setup_esram
- mov $POST_DEAD_CODE, %eax
-#if IS_ENABLED(CONFIG_POST_IO)
- outb %al, $CONFIG_POST_IO_PORT
-#else
- post_code(POST_DEAD_CODE)
-#endif
- jmp .
-
-setup_esram:
- /* Ensure cache is disabled. */
- movl %cr0, %eax
- orl $(CR0_CD | CR0_NW), %eax
- invd
- movl %eax, %cr0
-
- /*
- * Disable NMI operation
- * Good convention suggests you should read back RTC data port after
- * accessing the RTC index port.
- */
- movb $(NMI_DISABLE), %al
- movw $(RTC_INDEX), %dx
- outb %al, %dx
- movw $(RTC_DATA), %dx
- inb %dx, %al
-
- /* Disable SMI (Disables SMI wire, not SMI messages) */
- movl $((QUARK_OPCODE_READ << QNC_MCR_OP_OFFSET) \
- | (QUARK_NC_HOST_BRIDGE_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \
- | (QNC_MSG_FSBIC_REG_HMISC << QNC_MCR_REG_OFFSET)), %ecx
- leal L1, %esp
- jmp stackless_SideBand_Read
-L1:
- andl $(~SMI_EN), %eax
- movl $((QUARK_OPCODE_WRITE << QNC_MCR_OP_OFFSET) \
- | (QUARK_NC_HOST_BRIDGE_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \
- | (QNC_MSG_FSBIC_REG_HMISC << QNC_MCR_REG_OFFSET)), %ecx
- leal L2, %esp
- jmp stackless_SideBand_Write
-L2:
-
- /*
- * Before we get going, check SOC Unit Registers to see if we are
- * required to issue a warm/cold reset
- */
- movl $((QUARK_ALT_OPCODE_READ << QNC_MCR_OP_OFFSET) \
- | (QUARK_SCSS_SOC_UNIT_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \
- | (CFGNONSTICKY_W1_OFFSET << QNC_MCR_REG_OFFSET)), %ecx
- leal L3, %esp
- jmp stackless_SideBand_Read
-L3:
- andl $(FORCE_WARM_RESET), %eax
- jz TestForceColdReset /* No warm reset - branch */
- jmp IssueWarmReset
-
-TestForceColdReset:
- movl $((QUARK_ALT_OPCODE_READ << QNC_MCR_OP_OFFSET) \
- | (QUARK_SCSS_SOC_UNIT_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \
- | (CFGNONSTICKY_W1_OFFSET << QNC_MCR_REG_OFFSET)), %ecx
- leal L4, %esp
- jmp stackless_SideBand_Read
-L4:
- andl $(FORCE_COLD_RESET), %eax
- jz TestHmboundLock /* No cold reset - branch */
- jmp IssueColdReset
-
- /* Before setting HMBOUND, check it's not locked */
-TestHmboundLock:
- movl $((QUARK_OPCODE_READ << QNC_MCR_OP_OFFSET) \
- | (QUARK_NC_HOST_BRIDGE_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \
- | (HMBOUND_OFFSET << QNC_MCR_REG_OFFSET)), %ecx
- leal L5, %esp
- jmp stackless_SideBand_Read
-L5:
- andl $(HMBOUND_LOCK), %eax
- jz ConfigHmbound /* Good configuration - branch */
-
- /* Failed to config - store sticky bit debug */
- movl $((QUARK_ALT_OPCODE_READ << QNC_MCR_OP_OFFSET) \
- | (QUARK_SCSS_SOC_UNIT_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \
- | (CFGSTICKY_RW_OFFSET << QNC_MCR_REG_OFFSET)), %ecx
- leal L6, %esp
- jmp stackless_SideBand_Read
-L6:
- orl $(RESET_FOR_HMBOUND_LOCK), %eax
- movl $((QUARK_ALT_OPCODE_WRITE << QNC_MCR_OP_OFFSET) \
- | (QUARK_SCSS_SOC_UNIT_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \
- | (CFGSTICKY_RW_OFFSET << QNC_MCR_REG_OFFSET)), %ecx
- leal L7, %esp
- jmp stackless_SideBand_Write
-L7:
- jmp IssueWarmReset
-
- /* Set up the HMBOUND register */
-ConfigHmbound:
- movl $(HMBOUND_ADDRESS), %eax /* Data (Set HMBOUND location) */
- movl $((QUARK_OPCODE_WRITE << QNC_MCR_OP_OFFSET) \
- | (QUARK_NC_HOST_BRIDGE_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \
- | (HMBOUND_OFFSET << QNC_MCR_REG_OFFSET)), %ecx
- leal L8, %esp
- jmp stackless_SideBand_Write
-L8:
-
- /*
- * Enable interrupts to Remote Management Unit when a IMR/SMM/HMBOUND
- * violation occurs.
- */
- movl $(ENABLE_IMR_INTERRUPT), %eax /* Set interrupt enable mask */
- movl $((QUARK_OPCODE_WRITE << QNC_MCR_OP_OFFSET) \
- | (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \
- | (BIMRVCTL_OFFSET << QNC_MCR_REG_OFFSET)), %ecx
- leal L9, %esp
- jmp stackless_SideBand_Write
-L9:
-
- /* Move eSRAM memory to 2GB */
- movl $(ESRAM_ADDRESS_2G), %eax /* Data (Set eSRAM location) */
- movl $((QUARK_OPCODE_WRITE << QNC_MCR_OP_OFFSET) \
- | (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \
- | (QUARK_NC_MEMORY_MANAGER_ESRAMPGCTRL_BLOCK \
- << QNC_MCR_REG_OFFSET)), %ecx
- leal L10, %esp
- jmp stackless_SideBand_Write
-L10:
-
- /* Check that we're not blocked from setting the config that we want. */
- movl $((QUARK_OPCODE_READ << QNC_MCR_OP_OFFSET) \
- | (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \
- | (QUARK_NC_MEMORY_MANAGER_ESRAMPGCTRL_BLOCK \
- << QNC_MCR_REG_OFFSET)), %ecx
- leal L11, %esp
- jmp stackless_SideBand_Read
-L11:
- andl $(BLOCK_ENABLE_PG), %eax
- jnz ConfigPci /* Good configuration - branch */
-
- /* Failed to config - store sticky bit debug */
- movl $((QUARK_ALT_OPCODE_READ << QNC_MCR_OP_OFFSET) \
- | (QUARK_SCSS_SOC_UNIT_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \
- | (CFGSTICKY_RW_OFFSET << QNC_MCR_REG_OFFSET)), %ecx
- leal L12, %esp
- jmp stackless_SideBand_Read
-L12:
- orl $(RESET_FOR_ESRAM_LOCK), %eax
- movl $((QUARK_ALT_OPCODE_WRITE << QNC_MCR_OP_OFFSET) \
- | (QUARK_SCSS_SOC_UNIT_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \
- | (CFGSTICKY_RW_OFFSET << QNC_MCR_REG_OFFSET)), %ecx
- leal L13, %esp
- jmp stackless_SideBand_Write
-L13:
- jmp IssueWarmReset
-
- /* Enable PCIEXBAR */
-ConfigPci:
- movl $(EC_BASE + EC_ENABLE), %eax /* Data */
- movl $((QUARK_OPCODE_WRITE << QNC_MCR_OP_OFFSET) \
- | (QUARK_NC_MEMORY_ARBITER_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \
- | (AEC_CTRL_OFFSET << QNC_MCR_REG_OFFSET)), %ecx
- leal L14, %esp
- jmp stackless_SideBand_Write
-L14:
-
- movl $(EC_BASE + EC_ENABLE), %eax /* Data */
- movl $((QUARK_OPCODE_WRITE << QNC_MCR_OP_OFFSET) \
- | (QUARK_NC_HOST_BRIDGE_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \
- | (HECREG_OFFSET << QNC_MCR_REG_OFFSET)), %ecx
- leal L15, %esp
- jmp stackless_SideBand_Write
-L15:
-
- /* Open up full 8MB SPI decode */
- movl $(PCI_CFG | ILB_PFA | BDE), %ebx /* PCI config address */
- movl $(DECODE_ALL_REGIONS_ENABLE), %eax
- leal L16, %esp
- jmp stackless_PCIConfig_Write
-L16:
-
- jmp esram_init_done
-
-IssueWarmReset:
- /* Issue Warm Reset request to Remote Management Unit via iLB */
- movw $(CF9_WARM_RESET), %ax
- movw $(ILB_RESET_REG), %dx
- outw %ax, %dx
- jmp . /* Stay here until we are reset. */
-
-IssueColdReset:
- /* Issue Cold Reset request to Remote Management Unit via iLB */
- movw $(CF9_COLD_RESET), %ax
- movw $(ILB_RESET_REG), %dx
- outw %ax, %dx
- jmp . /* Stay here until we are reset. */
-
-/*
- *----------------------------------------------------------------------------
- *
- * Procedure: stackless_SideBand_Read
- *
- * Input: esp - return address
- * ecx[15:8] - Register offset
- * ecx[23:16] - Port ID
- * ecx[31:24] - Opcode
- *
- * Output: eax - Data read
- *
- * Destroys: eax
- * ebx
- * cl
- * esi
- *
- * Description:
- * Perform requested sideband read
- *----------------------------------------------------------------------------
- */
-
-stackless_SideBand_Read:
-
- movl %esp, %esi /* Save the return address */
-
- /* Load the SideBand Packet Register to generate the transaction */
- movl $(PCI_CFG | HOST_BRIDGE_PFA | QNC_ACCESS_PORT_MCR), %ebx
- movb $QNC_MCR_BYTE_ENABLES, %cl /* Set all Byte Enable bits */
- xchgl %ecx, %eax
- leal L17, %esp
- jmp stackless_PCIConfig_Write
-L17:
- xchgl %ecx, %eax
-
- /* Read the SideBand Data Register */
- movl $(PCI_CFG | HOST_BRIDGE_PFA | (QNC_ACCESS_PORT_MDR)), %ebx
- leal L18, %esp
- jmp stackless_PCIConfig_Read
-L18:
-
- movl %esi, %esp /* Restore the return address */
- RET32
-
-/*
- *----------------------------------------------------------------------------
- *
- * Procedure: stackless_SideBand_Write
- *
- * Input: esp - return address
- * eax - Data
- * ecx[15:8] - Register offset
- * ecx[23:16] - Port ID
- * ecx[31:24] - Opcode
- *
- * Output: None
- *
- * Destroys: ebx
- * cl
- * esi
- *
- * Description:
- * Perform requested sideband write
- *
- *----------------------------------------------------------------------------
- */
-
-stackless_SideBand_Write:
-
- movl %esp, %esi /* Save the return address */
-
- /* Load the SideBand Data Register with the data */
- movl $(PCI_CFG | HOST_BRIDGE_PFA | QNC_ACCESS_PORT_MDR), %ebx
- leal L19, %esp
- jmp stackless_PCIConfig_Write
-L19:
-
- /* Load the SideBand Packet Register to generate the transaction */
- movl $(PCI_CFG | HOST_BRIDGE_PFA | QNC_ACCESS_PORT_MCR), %ebx
- movb $QNC_MCR_BYTE_ENABLES, %cl /* Set all Byte Enable bits */
- xchgl %ecx, %eax
- leal L20, %esp
- jmp stackless_PCIConfig_Write
-L20:
- xchgl %ecx, %eax
-
- movl %esi, %esp /* Restore the return address */
- RET32
-
-/*
- *----------------------------------------------------------------------------
- *
- * Procedure: stackless_PCIConfig_Write
- *
- * Input: esp - return address
- * eax - Data to write
- * ebx - PCI Config Address
- *
- * Output: None
- *
- * Destroys: dx
- *
- * Description:
- * Perform a DWORD PCI Configuration write
- *
- *----------------------------------------------------------------------------
- */
-
-stackless_PCIConfig_Write:
-
- /* Write the PCI Config Address to the address port */
- xchgl %ebx, %eax
- movw $(PCI_ADDRESS_PORT), %dx
- outl %eax, %dx
- xchgl %ebx, %eax
-
- /* Write the PCI DWORD Data to the data port */
- movw $(PCI_DATA_PORT), %dx
- outl %eax, %dx
-
- RET32
-
-/*
- *----------------------------------------------------------------------------
- *
- * Procedure: stackless_PCIConfig_Read
- *
- * Input: esp - return address
- * ebx - PCI Config Address
- *
- * Output: eax - Data read
- *
- * Destroys: eax
- * dx
- *
- * Description:
- * Perform a DWORD PCI Configuration read
- *
- *----------------------------------------------------------------------------
- */
-
-stackless_PCIConfig_Read:
-
- /* Write the PCI Config Address to the address port */
- xchgl %ebx, %eax
- movw $(PCI_ADDRESS_PORT), %dx
- outl %eax, %dx
- xchgl %ebx, %eax
-
- /* Read the PCI DWORD Data from the data port */
- movw $(PCI_DATA_PORT), %dx
- inl %dx, %eax
-
- RET32
-
-/*----------------------------------------------------------------------------*/
-
-esram_init_done:
-
-#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1)
-
- /* Copy FSP image to eSRAM and call it. */
- /* TODO: FSP location/size could be got in a routine. */
- cld
- movl $(0x00040000), %ecx /* 256K DWORDs = 64K */
- shrl $2, %ecx
- movl $CONFIG_FSP_LOC, %esi /* The source address. */
- movl $CONFIG_FSP_ESRAM_LOC, %edi /* FSP destination in ESRAM */
- rep movsl
-#endif /* CONFIG_PLATFORM_USES_FSP1_1 */
-
-#if IS_ENABLED(CONFIG_ENABLE_DEBUG_LED)
-sd_led:
-
-.equ SD_PFA, (0x14 << 11) /* B0:D20:F0 - SDIO controller */
-.equ SD_CFG_BASE, (PCI_CFG | SD_PFA) /* SD cntrl base in PCI config space */
-.equ SD_CFG_CMD, (SD_CFG_BASE+0x04) /* Command reg in PCI config space */
-.equ SD_CFG_ADDR, (SD_CFG_BASE+0x10) /* Base address in PCI config space */
-.equ SD_BASE_ADDR, (0xA0018000) /* SD controller's base address */
-.equ SD_HOST_CTRL, (SD_BASE_ADDR+0x28) /* HOST_CTRL register */
-
- /* Set the SDIO controller's base address */
- movl $(SD_BASE_ADDR), %eax
- movl $(SD_CFG_ADDR), %ebx
- leal L40, %esp
- jmp stackless_PCIConfig_Write
-
-L40:
- movl $(SD_CFG_ADDR), %ebx
- leal L41, %esp
- jmp stackless_PCIConfig_Read
-
-L41:
- /* Enable the SDIO controller */
- movl $(SD_CFG_CMD), %ebx
- leal L42, %esp
- jmp stackless_PCIConfig_Read
-
-L42:
- orl $2, %eax
- movl $(SD_CFG_CMD), %ebx
- leal L43, %esp
- jmp stackless_PCIConfig_Write
-
-L43:
- movl $(SD_CFG_CMD), %ebx
- leal L44, %esp
- jmp stackless_PCIConfig_Read
-
-L44:
-#if IS_ENABLED(CONFIG_ENABLE_DEBUG_LED_ESRAM)
- /* Turn on SD LED to indicate ESRAM successfully initialized */
- movl $SD_HOST_CTRL, %ebx
- movb 0(%ebx), %al
- orb $1, %al
- movb %al, 0(%ebx)
-
- /* Loop forever */
- jmp .
-#endif /* CONFIG_ENABLE_DEBUG_LED_ESRAM */
-#endif /* CONFIG_ENABLE_DEBUG_LED */
diff --git a/src/soc/intel/quark/romstage/romstage.c b/src/soc/intel/quark/romstage/romstage.c
index 62f8b21..c14acb7 100644
--- a/src/soc/intel/quark/romstage/romstage.c
+++ b/src/soc/intel/quark/romstage/romstage.c
@@ -29,6 +29,7 @@
#include <soc/pm.h>
#include <soc/romstage.h>
#include <soc/reg_access.h>
+#include <string.h>
static const struct reg_script clear_smi_and_wake_events[] = {
/* Clear any SMI or wake events */
@@ -65,6 +66,33 @@ static const struct reg_script hsuart_init[] = {
REG_SCRIPT_END
};
+asmlinkage void *car_state_c_entry(void)
+{
+ post_code(0x20);
+ if (IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1)) {
+ FSP_INFO_HEADER *fih;
+ struct cache_as_ram_params car_params = {0};
+ void *top_of_stack;
+
+ /* Copy the FSP binary into ESRAM */
+ memcpy((void *)CONFIG_FSP_ESRAM_LOC, (void *)CONFIG_FSP_LOC,
+ 0x00040000);
+
+ /* Locate the FSP header in ESRAM */
+ fih = find_fsp(CONFIG_FSP_ESRAM_LOC);
+
+ /* Start the early verstage/romstage code */
+ post_code(0x2A);
+ car_params.fih = fih;
+ top_of_stack = cache_as_ram_main(&car_params);
+
+ /* Initialize MTRRs and switch stacks after RAM initialized */
+ return top_of_stack;
+ }
+
+ return NULL;
+}
+
void car_soc_pre_console_init(void)
{
/* Initialize the controllers */
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