[coreboot-gerrit] New patch to review for coreboot: pcengines/apu2: Add IVRS table generation

[Timothy Pearson (tpearson@raptorengineering.com)]

Timothy Pearson (tpearson at raptorengineering.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15165

-gerrit

commit 1db6a43f32d76dcad36b422610c4d0e569a6bb4a
Author: Timothy Pearson <tpearson at raptorengineering.com>
Date:   Mon Jun 13 13:49:36 2016 -0500

    pcengines/apu2: Add IVRS table generation
    
    The resultant IVRS tables have been tested and work with
    PCI passthrough under Xen.
    
    Change-Id: I81b5b421098f29163d6ae98527de152c8046b1d9
    Signed-off-by: Timothy Pearson <tpearson at raptorengineering.com>
---
 3rdparty/blobs                             |  2 +-
 src/mainboard/pcengines/apu2/acpi_tables.c | 38 ++++++++++++++++++++++++++++++
 2 files changed, 39 insertions(+), 1 deletion(-)

diff --git a/3rdparty/blobs b/3rdparty/blobs
index cca0337..b0eeddd 160000
--- a/3rdparty/blobs
+++ b/3rdparty/blobs
@@ -1 +1 @@
-Subproject commit cca0337ea0fba8a07a73ad1627338dd5738f4d3f
+Subproject commit b0eeddd4f5c583818e66521f2552cd3448b357b2
diff --git a/src/mainboard/pcengines/apu2/acpi_tables.c b/src/mainboard/pcengines/apu2/acpi_tables.c
index d5ebad4..c3e24c9 100644
--- a/src/mainboard/pcengines/apu2/acpi_tables.c
+++ b/src/mainboard/pcengines/apu2/acpi_tables.c
@@ -2,6 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * Copyright (C) 2016 Raptor Engineering, LLC
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -54,3 +55,40 @@ unsigned long acpi_fill_madt(unsigned long current)
 
 	return current;
 }
+
+unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t* ivrs, unsigned long current)
+{
+	uint8_t *p;
+
+	uint32_t apicid_sb800;
+	uint32_t apicid_northbridge;
+
+	apicid_sb800 = CONFIG_MAX_CPUS;
+	apicid_northbridge = CONFIG_MAX_CPUS + 1;
+
+	/* Describe NB IOAPIC */
+	p = (uint8_t *)current;
+	p[0] = 0x48;                    /* Entry type */
+	p[1] = 0;                       /* Device */
+	p[2] = 0;                       /* Bus */
+	p[3] = 0x0;                     /* Data */
+	p[4] = apicid_northbridge;      /* IOAPIC ID */
+	p[5] = 0x0;                     /* Device 0 Function 0 */
+	p[6] = 0x0;                     /* Northbridge bus */
+	p[7] = 0x1;                     /* Variety */
+	current += 8;
+
+	/* Describe SB IOAPIC */
+	p = (uint8_t *)current;
+	p[0] = 0x48;                    /* Entry type */
+	p[1] = 0;                       /* Device */
+	p[2] = 0;                       /* Bus */
+	p[3] = 0xd7;                    /* Data */
+	p[4] = apicid_sb800;            /* IOAPIC ID */
+	p[5] = 0x14 << 3;               /* Device 0x14 Function 0 */
+	p[6] = 0x0;                     /* Southbridge bus */
+	p[7] = 0x1;                     /* Variety */
+	current += 8;
+
+	return current;
+}