[coreboot-gerrit] Patch set updated for coreboot: DO NOT MERGE: lenovo/x60: Enable Infrared port.
Denis Carikli (GNUtoo@no-log.org)
gerrit at coreboot.org
Tue Jun 14 13:57:19 CEST 2016
Denis Carikli (GNUtoo at no-log.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/5242
-gerrit
commit bea228c2de23c0cea8e339c9c5bae59667609d2d
Author: Vladimir Serbinenko <phcoder at gmail.com>
Date: Sat Feb 15 19:13:00 2014 +0100
DO NOT MERGE: lenovo/x60: Enable Infrared port.
TODO:
- Re-test the modifications on the Lenovo X60T.
Here it was only compile-tested.
- More testing required: The only test that was
done (previously) was "ifconfig irda0 up" on the X60T.
- irda0 appears on the X60T but not on the X60.
Change-Id: I8ce0195bc85a983627826b31eb9879c3dbc80dd9
Signed-off-by: Vladimir Serbinenko <phcoder at gmail.com>
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo at no-log.org>
---
src/drivers/lenovo/lenovo.h | 3 ++-
src/drivers/lenovo/wacom.c | 40 +++++++++++++++++++++++++++++++++-
src/mainboard/lenovo/x200/mainboard.c | 2 +-
src/mainboard/lenovo/x201/mainboard.c | 2 +-
src/mainboard/lenovo/x60/devicetree.cb | 4 ++++
src/mainboard/lenovo/x60/mainboard.c | 2 +-
src/mainboard/lenovo/x60/romstage.c | 2 +-
src/superio/nsc/pc87382/chip.h | 24 ++++++++++++++++++++
src/superio/nsc/pc87382/pc87382.h | 11 ++++++++++
src/superio/nsc/pc87382/superio.c | 40 ++++++++++++++++++++++++++++++++++
10 files changed, 124 insertions(+), 6 deletions(-)
diff --git a/src/drivers/lenovo/lenovo.h b/src/drivers/lenovo/lenovo.h
index 4c44119..06b52e5 100644
--- a/src/drivers/lenovo/lenovo.h
+++ b/src/drivers/lenovo/lenovo.h
@@ -1,3 +1,4 @@
int drivers_lenovo_is_wacom_present(void);
void drivers_lenovo_serial_ports_ssdt_generate(const char *scope,
- int have_dock_serial);
+ int have_dock_serial,
+ int have_infrared);
diff --git a/src/drivers/lenovo/wacom.c b/src/drivers/lenovo/wacom.c
index d1464d7..1bc6ec2 100644
--- a/src/drivers/lenovo/wacom.c
+++ b/src/drivers/lenovo/wacom.c
@@ -87,7 +87,8 @@ drivers_lenovo_is_wacom_present(void)
void
drivers_lenovo_serial_ports_ssdt_generate(const char *scope,
- int have_dock_serial)
+ int have_dock_serial,
+ int have_infrared)
{
acpigen_write_scope(scope);
@@ -114,6 +115,43 @@ drivers_lenovo_serial_ports_ssdt_generate(const char *scope,
acpigen_pop_len();
}
+ if (have_infrared) {
+ /* Device op. */
+ acpigen_emit_byte(0x5b);
+ acpigen_emit_byte(0x82);
+ acpigen_write_len_f();
+ acpigen_emit_namestring("FIR");
+
+ acpigen_write_name("_HID");
+ acpigen_emit_eisaid("IBM0071");
+ acpigen_write_name("_CID");
+ acpigen_emit_eisaid("PNP0511");
+ acpigen_write_name("_UID");
+
+ /* One */
+ acpigen_write_byte(0x1);
+ acpigen_write_name("_CRS");
+
+ acpigen_write_resourcetemplate_header();
+ acpigen_write_io16(0x2f8, 0x2f8, 1, 8, 1);
+ acpigen_write_irq(0x08);
+
+ acpigen_write_resourcetemplate_footer();
+
+ /* method op */
+ acpigen_emit_byte(0x14);
+ acpigen_write_len_f();
+ acpigen_emit_namestring("_STA");
+ /* no fnarg */
+ acpigen_emit_byte(0x00);
+ /* return */
+ acpigen_emit_byte(0xa4);
+ acpigen_write_byte(0xf);
+ acpigen_pop_len();
+
+ acpigen_pop_len();
+ }
+
if (have_dock_serial) {
acpigen_write_device("COMA");
diff --git a/src/mainboard/lenovo/x200/mainboard.c b/src/mainboard/lenovo/x200/mainboard.c
index bcf5f3e..e14b2b3 100644
--- a/src/mainboard/lenovo/x200/mainboard.c
+++ b/src/mainboard/lenovo/x200/mainboard.c
@@ -30,7 +30,7 @@
static void fill_ssdt(device_t device)
{
- drivers_lenovo_serial_ports_ssdt_generate("\\_SB.PCI0.LPCB", 0);
+ drivers_lenovo_serial_ports_ssdt_generate("\\_SB.PCI0.LPCB", 0, 0);
}
static void mainboard_enable(device_t dev)
diff --git a/src/mainboard/lenovo/x201/mainboard.c b/src/mainboard/lenovo/x201/mainboard.c
index 2f35c81..0f24f0e 100644
--- a/src/mainboard/lenovo/x201/mainboard.c
+++ b/src/mainboard/lenovo/x201/mainboard.c
@@ -85,7 +85,7 @@ static void mainboard_init(device_t dev)
static void fill_ssdt(device_t device)
{
- drivers_lenovo_serial_ports_ssdt_generate("\\_SB.PCI0.LPCB", 0);
+ drivers_lenovo_serial_ports_ssdt_generate("\\_SB.PCI0.LPCB", 0, 0);
}
static void mainboard_enable(device_t dev)
diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb
index e2a24c1..82c411b 100644
--- a/src/mainboard/lenovo/x60/devicetree.cb
+++ b/src/mainboard/lenovo/x60/devicetree.cb
@@ -131,6 +131,7 @@ chip northbridge/intel/i945
chip superio/nsc/pc87382
device pnp 164e.2 on # IR
io 0x60 = 0x2f8
+ irq 0x70 = 0x3
end
device pnp 164e.3 on # Digitizer
@@ -147,6 +148,9 @@ chip northbridge/intel/i945
device pnp 164e.19 on # DLPC
io 0x60 = 0x164c
end
+
+ register "ir_enable" = "1"
+
end
chip superio/nsc/pc87392
diff --git a/src/mainboard/lenovo/x60/mainboard.c b/src/mainboard/lenovo/x60/mainboard.c
index 5ea4221..8f007a1 100644
--- a/src/mainboard/lenovo/x60/mainboard.c
+++ b/src/mainboard/lenovo/x60/mainboard.c
@@ -97,7 +97,7 @@ static void mainboard_init(device_t dev)
static void fill_ssdt(device_t device)
{
- drivers_lenovo_serial_ports_ssdt_generate("\\_SB.PCI0.LPCB", 1);
+ drivers_lenovo_serial_ports_ssdt_generate("\\_SB.PCI0.LPCB", 1, 1);
}
static void mainboard_enable(device_t dev)
diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c
index a60e056..ad1c5e3 100644
--- a/src/mainboard/lenovo/x60/romstage.c
+++ b/src/mainboard/lenovo/x60/romstage.c
@@ -83,7 +83,7 @@ static void ich7_enable_lpc(void)
// decode range
pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0210);
// decode range
- pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x1f0d);
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x1f0f);
/* range 0x1600 - 0x167f */
pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x84, 0x1601);
diff --git a/src/superio/nsc/pc87382/chip.h b/src/superio/nsc/pc87382/chip.h
new file mode 100644
index 0000000..1bc1c96
--- /dev/null
+++ b/src/superio/nsc/pc87382/chip.h
@@ -0,0 +1,24 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Denis 'GNUtoo' Carikli <GNUtoo at no-log.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SUPERIO_NSC_PC87382_CHIP_H
+#define SUPERIO_NSC_PC87382_CHIP_H
+
+struct superio_nsc_pc87382_config {
+ u8 ir_enable;
+};
+
+#endif /* SUPERIO_NSC_PC87382_CHIP_H */
diff --git a/src/superio/nsc/pc87382/pc87382.h b/src/superio/nsc/pc87382/pc87382.h
index 6826f45..a5cbdcc 100644
--- a/src/superio/nsc/pc87382/pc87382.h
+++ b/src/superio/nsc/pc87382/pc87382.h
@@ -21,4 +21,15 @@
#define PC87382_SP1 0x03
#define PC87382_GPIO 0x07
#define PC87382_DOCK 0x19
+
+#define PC87382_CLOCKCF_REG 0x29
+#define PC87382_DMA_CHAN_SELECT_0_REG 0x74
+#define PC87382_IR_CONF_REG 0x0f
+
+#define PC87382_IR_LOW_POWER_MODE (0 << 1)
+#define PC87382_IR_NORMAL_POWER_MODE (1 << 1)
+#define PC87382_IR_BANK_SELECT_ENABLE (1 << 7)
+
+#define PC87382_DMA_CHANNEL(chan_nr) (chan_nr << 0)
+
#endif
diff --git a/src/superio/nsc/pc87382/superio.c b/src/superio/nsc/pc87382/superio.c
index 377107e..e75a75e 100644
--- a/src/superio/nsc/pc87382/superio.c
+++ b/src/superio/nsc/pc87382/superio.c
@@ -22,19 +22,59 @@
#include <pc80/keyboard.h>
#include <stdlib.h>
#include "pc87382.h"
+#include "chip.h"
+
+static void pc8732_enable_ir(struct device *dev, bool enable)
+{
+ if (enable) {
+ u16 tmp;
+ /* TODO: Check if really needed */
+ /* 0001 1110 -> CKVALID LOCKCCF|RESERVED*/
+ /* 1011 0000 -> CKEN|0|CK48SEL|CKVALID */
+ /* pnp_write_config(dev, PC87382_CLOCKCF_REG, 0xb0); */
+
+ /* Set DMA channel */
+ tmp = pnp_read_config(dev,
+ PC87382_DMA_CHAN_SELECT_0_REG);
+ tmp |= PC87382_DMA_CHANNEL(1);
+ pnp_write_config(dev, PC87382_DMA_CHAN_SELECT_0_REG,
+ 0x01);
+
+ /* TODO: check if we really need the NORMAL_POWER_MODE */
+ tmp = pnp_read_config(dev, PC87382_IR_CONF_REG);
+ tmp |= (PC87382_IR_NORMAL_POWER_MODE |
+ PC87382_IR_BANK_SELECT_ENABLE);
+ pnp_write_config(dev, PC87382_IR_CONF_REG, 0x82);
+ } else {
+ /* TODO: check if needed */
+ // pnp_write_config(dev, PC87382_CLOCKCF_REG, 0x00);
+ pnp_write_config(dev, PC87382_DMA_CHAN_SELECT_0_REG,
+ 0x04);
+ pnp_write_config(dev, PC87382_IR_CONF_REG, 0x02);
+ }
+}
static void init(struct device *dev)
{
+ struct superio_nsc_pc87382_config *conf = dev->chip_info;
+
if (!dev->enabled)
return;
+ pnp_enter_conf_mode(dev);
+
switch(dev->path.pnp.device) {
+ case PC87382_IR:
+ pc8732_enable_ir(dev, !!(conf->ir_enable));
+ break;
case PC87382_DOCK:
break;
case PC87382_GPIO:
break;
}
+
+ pnp_exit_conf_mode(dev);
}
static struct device_operations ops = {
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