[coreboot-gerrit] New patch to review for coreboot: nb/intel/sandybridge/raminit: Code cleanup

[Patrick Rudolph (siro@das-labor.org)]

Patrick Rudolph (siro at das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15181

-gerrit

commit 4da7de4b17797e83ef93ce895ec07ac5523ff50a
Author: Patrick Rudolph <siro at das-labor.org>
Date:   Tue Jun 14 18:44:28 2016 +0200

    nb/intel/sandybridge/raminit: Code cleanup
    
    Simplify calculation of value.
    
    Change-Id: I3ecd12c431b46a8d2218f33d7eb3e10de3bcd61d
    Signed-off-by: Patrick Rudolph <siro at das-labor.org>
---
 src/northbridge/intel/sandybridge/raminit.c | 9 +++------
 1 file changed, 3 insertions(+), 6 deletions(-)

diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c
index 9b0dfa6..49cffc2 100644
--- a/src/northbridge/intel/sandybridge/raminit.c
+++ b/src/northbridge/intel/sandybridge/raminit.c
@@ -656,7 +656,6 @@ static void dram_timing(ramctr_timing * ctrl)
 		ctrl->timC_offset[1] = 7;
 		ctrl->timC_offset[2] = 7;
 		ctrl->reg_c14_offset = 16;
-		ctrl->reg_5064b0 = 0x218;
 		ctrl->reg_320c_range_threshold = 13;
 	} else if (ctrl->tCK <= TCK_933MHZ) {
 		ctrl->tCK = TCK_933MHZ;
@@ -667,7 +666,6 @@ static void dram_timing(ramctr_timing * ctrl)
 		ctrl->timC_offset[1] = 6;
 		ctrl->timC_offset[2] = 6;
 		ctrl->reg_c14_offset = 14;
-		ctrl->reg_5064b0 = 0x1d5;
 		ctrl->reg_320c_range_threshold = 15;
 	} else if (ctrl->tCK <= TCK_800MHZ) {
 		ctrl->tCK = TCK_800MHZ;
@@ -678,7 +676,6 @@ static void dram_timing(ramctr_timing * ctrl)
 		ctrl->timC_offset[1] = 5;
 		ctrl->timC_offset[2] = 5;
 		ctrl->reg_c14_offset = 12;
-		ctrl->reg_5064b0 = 0x193;
 		ctrl->reg_320c_range_threshold = 15;
 	} else if (ctrl->tCK <= TCK_666MHZ) {
 		ctrl->tCK = TCK_666MHZ;
@@ -689,7 +686,6 @@ static void dram_timing(ramctr_timing * ctrl)
 		ctrl->timC_offset[1] = 4;
 		ctrl->timC_offset[2] = 4;
 		ctrl->reg_c14_offset = 10;
-		ctrl->reg_5064b0 = 0x150;
 		ctrl->reg_320c_range_threshold = 16;
 	} else if (ctrl->tCK <= TCK_533MHZ) {
 		ctrl->tCK = TCK_533MHZ;
@@ -700,7 +696,6 @@ static void dram_timing(ramctr_timing * ctrl)
 		ctrl->timC_offset[1] = 3;
 		ctrl->timC_offset[2] = 3;
 		ctrl->reg_c14_offset = 8;
-		ctrl->reg_5064b0 = 0x10d;
 		ctrl->reg_320c_range_threshold = 17;
 	} else  {
 		ctrl->tCK = TCK_400MHZ;
@@ -711,10 +706,12 @@ static void dram_timing(ramctr_timing * ctrl)
 		ctrl->timC_offset[1] = 2;
 		ctrl->timC_offset[2] = 2;
 		ctrl->reg_c14_offset = 8;
-		ctrl->reg_5064b0 = 0xcd;
 		ctrl->reg_320c_range_threshold = 17;
 	}
 
+	/* DLL_CONFIG_MDLL_W_TIMER */
+	ctrl->reg_5064b0 = (128000 / ctrl->tCK) + 3;
+
 	val32 = (1000 << 8) / ctrl->tCK;
 	printk(BIOS_DEBUG, "Selected DRAM frequency: %u MHz\n", val32);