[coreboot-gerrit] New patch to review for coreboot: nb/intel/sandybridge/raminit: Set phase coding for CLK pins

[Patrick Rudolph (siro@das-labor.org)]

Patrick Rudolph (siro at das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15184

-gerrit

commit f3af210310f2b281cb80e848afe2427d211a626f
Author: Patrick Rudolph <siro at das-labor.org>
Date:   Tue Jun 14 20:07:32 2016 +0200

    nb/intel/sandybridge/raminit: Set phase coding for CLK pins
    
    Set the phase coding for CLK pins.
    The mrc sets the same values depending on DDR frequency.
    
    Change-Id: I57ffbfeb291fc2fede278d18527993e7432e9bd8
    Signed-off-by: Patrick Rudolph <siro at das-labor.org>
---
 src/northbridge/intel/sandybridge/raminit.c | 20 +++++++++++++++++---
 1 file changed, 17 insertions(+), 3 deletions(-)

diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c
index 49cffc2..49fae2e 100644
--- a/src/northbridge/intel/sandybridge/raminit.c
+++ b/src/northbridge/intel/sandybridge/raminit.c
@@ -617,9 +617,23 @@ static u32 get_COMP2(u32 tCK)
 	return frq_comp2_map[get_FRQ(tCK) - 3];
 }
 
-static u32 get_XOVER_CLK(u8 rankmap)
+static u32 get_XOVER_CLK(ramctr_timing *ctrl, int channel)
 {
-	return rankmap << 24;
+	u32 reg = 0;
+	u32 pi;
+	int slotrank;
+
+	/* set PI coding for DDR CLK pins */
+	pi = (256000 / tCK) / 133;
+
+	FOR_ALL_POPULATED_RANKS {
+		reg |= pi << (slotrank * 6);
+	}
+
+	/* CLK xover enable */
+	reg |= ctrl->rankmap[channel] << 24;
+
+	return reg;
 }
 
 static u32 get_XOVER_CMD(u8 rankmap)
@@ -848,7 +862,7 @@ static void dram_xover(ramctr_timing * ctrl)
 
 	FOR_ALL_CHANNELS {
 		// enable xover clk
-		reg = get_XOVER_CLK(ctrl->rankmap[channel]);
+		reg = get_XOVER_CLK(ctrl, channel);
 		printram("XOVER CLK [%x] = %x\n", channel * 0x100 + 0xc14,
 			 reg);
 		MCHBAR32(channel * 0x100 + 0xc14) = reg;